[15:49:47.004] INFO: === Welcome to pxar ===
[15:49:47.004] INFO: === Today: 2015/09/10
[15:49:47.004] INFO: readRocDacs: M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C0.dat .. M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C15.dat
[15:49:47.005] INFO: readTbmDacs: M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/tbmParameters_C0a.dat .. M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/tbmParameters_C0b.dat
[15:49:47.005] INFO: readMaskFile: M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/defaultMaskFile.dat
[15:49:47.005] INFO: readTrimFile: M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters_C0.dat .. M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters_C15.dat
[15:49:47.079] INFO: clk: 4
[15:49:47.079] INFO: ctr: 4
[15:49:47.079] INFO: sda: 19
[15:49:47.079] INFO: tin: 9
[15:49:47.079] INFO: level: 15
[15:49:47.079] INFO: triggerdelay: 0
[15:49:47.079] QUIET: Instanciating API for pxar prod-10+20~g6580e80
[15:49:47.079] INFO: Log level: INFO
[15:49:47.088] INFO: Found DTB DTB_WS8ZAW
[15:49:47.101] QUIET: Connection to board DTB_WS8ZAW opened.
[15:49:47.107] INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 85
HW version: DTB1.2
FW version: 4.2
SW version: 4.4
USB id: DTB_WS8ZAW
MAC address: 40D855118055
Hostname: pixelDTB085
Comment:
------------------------------------------------------
[15:49:47.110] INFO: RPC call hashes of host and DTB match: 397073690
[15:49:48.715] INFO: DUT info:
[15:49:48.715] INFO: The DUT currently contains the following objects:
[15:49:48.715] INFO: 2 TBM Cores tbm08c (2 ON)
[15:49:48.715] INFO: TBM Core alpha (0): 7 registers set
[15:49:48.715] INFO: TBM Core beta (1): 7 registers set
[15:49:48.715] INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[15:49:48.715] INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.715] INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.715] INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:48.716] INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[15:49:49.117] INFO: enter 'restricted' command line mode
[15:49:49.117] INFO: enter test to run
[15:49:49.117] INFO: test: Pretest no parameter change
[15:49:49.117] INFO: running: pretest
[15:49:49.123] INFO: ######################################################################
[15:49:49.123] INFO: PixTestPretest::doTest()
[15:49:49.123] INFO: ######################################################################
[15:49:49.125] INFO: ----------------------------------------------------------------------
[15:49:49.125] INFO: PixTestPretest::programROC()
[15:49:49.125] INFO: ----------------------------------------------------------------------
[15:50:07.143] INFO: PixTestPretest::programROC() done: ROCs are all programmable
[15:50:07.143] INFO: IA differences per ROC: 17.7 16.9 20.1 18.5 18.5 17.7 19.3 18.5 16.9 17.7 18.5 16.9 21.7 20.1 19.3 18.5
[15:50:07.200] INFO: ----------------------------------------------------------------------
[15:50:07.200] INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[15:50:07.200] INFO: ----------------------------------------------------------------------
[15:50:11.279] INFO: PixTestPretest::setVana() done, Module Ia 380.2 mA = 23.7625 mA/ROC
[15:50:11.281] INFO: ----------------------------------------------------------------------
[15:50:11.281] INFO: PixTestPretest::findTiming()
[15:50:11.281] INFO: ----------------------------------------------------------------------
[15:50:11.281] INFO: PixTestCmd::init()
[15:50:11.908] WARNING: Not unmasking DUT, not setting Calibrate bits!
[15:51:45.087] INFO: TBM phases: 160MHz: 7, 400MHz: 2, TBM delays: ROC(0/1):4, header/trailer: 1, token: 1
[15:51:45.087] INFO: (success/tries = 100/100), width = 4
[15:51:45.089] INFO: ----------------------------------------------------------------------
[15:51:45.089] INFO: PixTestPretest::findWorkingPixel()
[15:51:45.089] INFO: ----------------------------------------------------------------------
[15:51:45.228] INFO: Expecting 231680 events.
[15:51:50.418] ERROR: <datapipe.cc/CheckEventValidity:L480> Channel 0 Number of ROCs (1) != Token Chain Length (8)
[15:51:50.420] ERROR: <datapipe.cc/CheckEventID:L453> Channel 0 Event ID mismatch: local ID (21) != TBM ID (2)
[15:51:53.117] INFO: 231680 events read in total (7111ms).
[15:51:53.121] INFO: Test took 8030ms.
[15:51:53.592] INFO: Found working pixel in all ROCs: col/row = 12/22
[15:51:53.634] INFO: ----------------------------------------------------------------------
[15:51:53.634] INFO: PixTestPretest::setVthrCompCalDel()
[15:51:53.634] INFO: ----------------------------------------------------------------------
[15:51:53.771] INFO: Expecting 231680 events.
[15:52:01.699] INFO: 231680 events read in total (7149ms).
[15:52:01.704] INFO: Test took 8065ms.
[15:52:02.182] INFO: PixTestPretest::setVthrCompCalDel() done
[15:52:02.182] INFO: CalDel: 109 105 132 128 138 117 126 109 130 121 111 126 139 143 141 117
[15:52:02.182] INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[15:52:02.185] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C0.dat
[15:52:02.186] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C1.dat
[15:52:02.186] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C2.dat
[15:52:02.186] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C3.dat
[15:52:02.186] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C4.dat
[15:52:02.186] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C5.dat
[15:52:02.187] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C6.dat
[15:52:02.187] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C7.dat
[15:52:02.187] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C8.dat
[15:52:02.187] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C9.dat
[15:52:02.187] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C10.dat
[15:52:02.188] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C11.dat
[15:52:02.188] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C12.dat
[15:52:02.188] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C13.dat
[15:52:02.188] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C14.dat
[15:52:02.188] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters_C15.dat
[15:52:02.189] INFO: write tbm parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/tbmParameters_C0a.dat
[15:52:02.189] INFO: write tbm parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/tbmParameters_C0b.dat
[15:52:02.189] INFO: PixTestPretest::doTest() done, duration: 133 seconds
[15:52:02.256] INFO: enter test to run
[15:52:02.256] INFO: test: FullTest no parameter change
[15:52:02.256] INFO: running: fulltest
[15:52:02.256] INFO: ######################################################################
[15:52:02.256] INFO: PixTestFullTest::doTest()
[15:52:02.256] INFO: ######################################################################
[15:52:02.257] INFO: ######################################################################
[15:52:02.257] INFO: PixTestAlive::doTest()
[15:52:02.257] INFO: ######################################################################
[15:52:02.259] INFO: ----------------------------------------------------------------------
[15:52:02.259] INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:52:02.259] INFO: ----------------------------------------------------------------------
[15:52:02.615] INFO: Expecting 41600 events.
[15:52:06.768] INFO: 41600 events read in total (3374ms).
[15:52:06.768] INFO: Test took 4507ms.
[15:52:06.774] INFO: Fetched DAQ statistics. Counters are being reset now.
[15:52:07.220] INFO: PixTestAlive::aliveTest() done
[15:52:07.220] INFO: number of dead pixels per ROC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:52:07.221] INFO: ----------------------------------------------------------------------
[15:52:07.221] INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:52:07.221] INFO: ----------------------------------------------------------------------
[15:52:07.576] INFO: Expecting 41600 events.
[15:52:10.506] INFO: 41600 events read in total (2151ms).
[15:52:10.506] INFO: Test took 3283ms.
[15:52:10.506] INFO: Fetched DAQ statistics. Counters are being reset now.
[15:52:10.506] INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[15:52:10.973] INFO: PixTestAlive::maskTest() done
[15:52:10.973] INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:52:10.975] INFO: ----------------------------------------------------------------------
[15:52:10.975] INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[15:52:10.975] INFO: ----------------------------------------------------------------------
[15:52:11.325] INFO: Expecting 41600 events.
[15:52:15.445] INFO: 41600 events read in total (3342ms).
[15:52:15.445] INFO: Test took 4469ms.
[15:52:15.451] INFO: Fetched DAQ statistics. Counters are being reset now.
[15:52:15.893] INFO: PixTestAlive::addressDecodingTest() done
[15:52:15.893] INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:52:15.893] INFO: PixTestAlive::doTest() done, duration: 13 seconds
[15:52:15.899] INFO: ######################################################################
[15:52:15.899] INFO: PixTestBBMap::doTest() Ntrig = 16, VcalS = 250 (high range)
[15:52:15.899] INFO: ######################################################################
[15:52:15.901] INFO: ---> dac: VthrComp name: calSMap ntrig: 16 dacrange: 0 .. 149 (-1/-1) hits flags = 2 (plus default)
[15:52:15.938] INFO: dacScan split into 1 runs with ntrig = 16
[15:52:15.938] INFO: run 1 of 1
[15:52:16.286] INFO: Expecting 9984000 events.
[15:52:44.544] INFO: 1234352 events read in total (27479ms).
[15:53:11.941] INFO: 2451984 events read in total (54877ms).
[15:53:38.943] INFO: 3652208 events read in total (81879ms).
[15:54:05.912] INFO: 4837424 events read in total (108847ms).
[15:54:32.878] INFO: 6027616 events read in total (135814ms).
[15:54:59.939] INFO: 7225968 events read in total (162874ms).
[15:55:27.103] INFO: 8433040 events read in total (190038ms).
[15:55:54.260] INFO: 9646496 events read in total (217195ms).
[15:56:02.161] INFO: 9984000 events read in total (225096ms).
[15:56:02.205] INFO: Test took 226268ms.
[15:56:02.297] INFO: Fetched DAQ statistics. Counters are being reset now.
[15:56:23.191] INFO: PixTestBBMap::doTest() done, duration: 247 seconds
[15:56:23.192] INFO: number of dead bumps (per ROC): 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0
[15:56:23.192] INFO: separation cut (per ROC): 130 120 121 115 113 123 113 123 106 103 110 102 121 108 102 102
[15:56:23.268] INFO: ######################################################################
[15:56:23.268] INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[15:56:23.268] INFO: ######################################################################
[15:56:23.268] INFO: ----------------------------------------------------------------------
[15:56:23.268] INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[15:56:23.268] INFO: ----------------------------------------------------------------------
[15:56:23.268] INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 0 .. 149 (-1/-1) hits flags = 16 (plus default)
[15:56:23.281] INFO: dacScan split into 1 runs with ntrig = 50
[15:56:23.281] INFO: run 1 of 1
[15:56:23.632] INFO: Expecting 31200000 events.
[15:56:46.836] INFO: 1237450 events read in total (22423ms).
[15:57:10.735] INFO: 2458300 events read in total (46323ms).
[15:57:34.576] INFO: 3674450 events read in total (70163ms).
[15:57:58.372] INFO: 4888350 events read in total (93959ms).
[15:58:22.164] INFO: 6098600 events read in total (117751ms).
[15:58:45.904] INFO: 7310500 events read in total (141491ms).
[15:59:09.613] INFO: 8516050 events read in total (165200ms).
[15:59:33.315] INFO: 9720000 events read in total (188902ms).
[15:59:56.911] INFO: 10924900 events read in total (212498ms).
[16:00:20.479] INFO: 12123100 events read in total (236066ms).
[16:00:44.024] INFO: 13319900 events read in total (259611ms).
[16:01:07.516] INFO: 14518200 events read in total (283103ms).
[16:01:30.976] INFO: 15709550 events read in total (306563ms).
[16:01:54.357] INFO: 16888250 events read in total (329944ms).
[16:02:17.671] INFO: 18062500 events read in total (353258ms).
[16:02:40.953] INFO: 19235400 events read in total (376540ms).
[16:03:04.263] INFO: 20405150 events read in total (399850ms).
[16:03:27.530] INFO: 21572150 events read in total (423117ms).
[16:03:50.798] INFO: 22737250 events read in total (446385ms).
[16:04:14.124] INFO: 23901050 events read in total (469711ms).
[16:04:37.451] INFO: 25064150 events read in total (493038ms).
[16:05:00.799] INFO: 26228250 events read in total (516386ms).
[16:05:24.172] INFO: 27391750 events read in total (539759ms).
[16:05:47.543] INFO: 28557300 events read in total (563130ms).
[16:06:10.820] INFO: 29722450 events read in total (586407ms).
[16:06:34.427] INFO: 30904050 events read in total (610014ms).
[16:06:39.942] INFO: 31200000 events read in total (615529ms).
[16:06:39.974] INFO: Test took 616693ms.
[16:06:40.060] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:06:40.256] INFO: dumping ASCII scurve output file: SCurveData
[16:06:41.681] INFO: dumping ASCII scurve output file: SCurveData
[16:06:43.114] INFO: dumping ASCII scurve output file: SCurveData
[16:06:44.593] INFO: dumping ASCII scurve output file: SCurveData
[16:06:46.051] INFO: dumping ASCII scurve output file: SCurveData
[16:06:47.520] INFO: dumping ASCII scurve output file: SCurveData
[16:06:48.965] INFO: dumping ASCII scurve output file: SCurveData
[16:06:50.437] INFO: dumping ASCII scurve output file: SCurveData
[16:06:51.884] INFO: dumping ASCII scurve output file: SCurveData
[16:06:53.383] INFO: dumping ASCII scurve output file: SCurveData
[16:06:54.924] INFO: dumping ASCII scurve output file: SCurveData
[16:06:56.469] INFO: dumping ASCII scurve output file: SCurveData
[16:06:58.009] INFO: dumping ASCII scurve output file: SCurveData
[16:06:59.456] INFO: dumping ASCII scurve output file: SCurveData
[16:07:00.940] INFO: dumping ASCII scurve output file: SCurveData
[16:07:02.417] INFO: dumping ASCII scurve output file: SCurveData
[16:07:03.941] INFO: PixTestScurves::scurves() done
[16:07:03.941] INFO: Vcal mean: 101.27 101.41 95.30 101.05 91.47 99.85 84.01 106.64 91.73 91.36 96.12 90.74 105.86 94.32 93.54 87.77
[16:07:03.941] INFO: Vcal RMS: 5.16 5.17 5.09 5.24 5.24 5.20 4.93 5.41 6.02 5.87 5.23 5.40 5.30 5.43 6.36 5.71
[16:07:03.941] INFO: PixTestScurves::fullTest() done, duration: 640 seconds
[16:07:04.012] INFO: ######################################################################
[16:07:04.012] INFO: PixTestTrim::doTest()
[16:07:04.012] INFO: ######################################################################
[16:07:04.013] INFO: ----------------------------------------------------------------------
[16:07:04.013] INFO: PixTestTrim::trimTest() ntrig = 20, vcal = 35
[16:07:04.013] INFO: ----------------------------------------------------------------------
[16:07:04.084] INFO: ---> VthrComp thr map (minimal VthrComp)
[16:07:04.084] INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[16:07:04.094] INFO: dacScan split into 1 runs with ntrig = 20
[16:07:04.094] INFO: run 1 of 1
[16:07:04.443] INFO: Expecting 13312000 events.
[16:07:33.549] INFO: 1458120 events read in total (28327ms).
[16:08:01.848] INFO: 2908520 events read in total (56626ms).
[16:08:29.056] INFO: 4354980 events read in total (83834ms).
[16:08:57.218] INFO: 5793040 events read in total (111996ms).
[16:09:25.417] INFO: 7229300 events read in total (140196ms).
[16:09:53.767] INFO: 8677880 events read in total (168545ms).
[16:10:22.126] INFO: 10130260 events read in total (196904ms).
[16:10:50.565] INFO: 11584260 events read in total (225343ms).
[16:11:18.819] INFO: 13042220 events read in total (253597ms).
[16:11:24.033] INFO: 13312000 events read in total (258811ms).
[16:11:24.063] INFO: Test took 259969ms.
[16:11:24.117] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:11:43.102] INFO: ROC 0 VthrComp = 102
[16:11:43.102] INFO: ROC 1 VthrComp = 102
[16:11:43.102] INFO: ROC 2 VthrComp = 97
[16:11:43.102] INFO: ROC 3 VthrComp = 96
[16:11:43.102] INFO: ROC 4 VthrComp = 91
[16:11:43.102] INFO: ROC 5 VthrComp = 101
[16:11:43.102] INFO: ROC 6 VthrComp = 87
[16:11:43.103] INFO: ROC 7 VthrComp = 103
[16:11:43.103] INFO: ROC 8 VthrComp = 89
[16:11:43.103] INFO: ROC 9 VthrComp = 89
[16:11:43.103] INFO: ROC 10 VthrComp = 96
[16:11:43.103] INFO: ROC 11 VthrComp = 91
[16:11:43.104] INFO: ROC 12 VthrComp = 105
[16:11:43.104] INFO: ROC 13 VthrComp = 94
[16:11:43.104] INFO: ROC 14 VthrComp = 92
[16:11:43.104] INFO: ROC 15 VthrComp = 88
[16:11:43.104] INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[16:11:43.104] INFO: ---> dac: vcal name: TrimThr1 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[16:11:43.114] INFO: dacScan split into 1 runs with ntrig = 20
[16:11:43.114] INFO: run 1 of 1
[16:11:43.464] INFO: Expecting 13312000 events.
[16:12:06.662] INFO: 917040 events read in total (22419ms).
[16:12:29.961] INFO: 1831280 events read in total (45718ms).
[16:12:53.219] INFO: 2743700 events read in total (68976ms).
[16:13:16.557] INFO: 3657460 events read in total (92314ms).
[16:13:39.858] INFO: 4571140 events read in total (115615ms).
[16:14:03.198] INFO: 5486220 events read in total (138955ms).
[16:14:26.529] INFO: 6401620 events read in total (162286ms).
[16:14:49.807] INFO: 7310300 events read in total (185564ms).
[16:15:13.101] INFO: 8215780 events read in total (208858ms).
[16:15:36.321] INFO: 9118400 events read in total (232078ms).
[16:15:59.543] INFO: 10020360 events read in total (255300ms).
[16:16:22.807] INFO: 10920700 events read in total (278564ms).
[16:16:46.209] INFO: 11822120 events read in total (301966ms).
[16:17:09.520] INFO: 12722520 events read in total (325277ms).
[16:17:24.489] INFO: 13312000 events read in total (340246ms).
[16:17:24.547] INFO: Test took 341433ms.
[16:17:24.714] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:17:49.813] INFO: roc 0 with ID = 0 has maximal Vcal 57.4418 for pixel 10/8 mean/min/max = 44.6243/31.7851/57.4635
[16:17:49.813] INFO: roc 1 with ID = 1 has maximal Vcal 57.3025 for pixel 46/3 mean/min/max = 44.5152/31.7055/57.3248
[16:17:49.813] INFO: roc 2 with ID = 2 has maximal Vcal 57.6045 for pixel 20/0 mean/min/max = 44.5624/31.4423/57.6824
[16:17:49.814] INFO: roc 3 with ID = 3 has maximal Vcal 58.4402 for pixel 11/26 mean/min/max = 45.6651/32.88/58.4502
[16:17:49.814] INFO: roc 4 with ID = 4 has maximal Vcal 58.4483 for pixel 3/4 mean/min/max = 46.2851/34.1095/58.4608
[16:17:49.814] INFO: roc 5 with ID = 5 has maximal Vcal 57.2677 for pixel 49/79 mean/min/max = 44.6698/32.0458/57.2937
[16:17:49.814] INFO: roc 6 with ID = 6 has maximal Vcal 57.2654 for pixel 8/11 mean/min/max = 44.8137/32.2038/57.4236
[16:17:49.815] INFO: roc 7 with ID = 7 has maximal Vcal 58.5474 for pixel 14/34 mean/min/max = 45.9968/33.275/58.7186
[16:17:49.815] INFO: roc 8 with ID = 8 has maximal Vcal 60.1132 for pixel 5/24 mean/min/max = 47.2211/34.0861/60.3561
[16:17:49.815] INFO: roc 9 with ID = 9 has maximal Vcal 60.5206 for pixel 0/57 mean/min/max = 47.0252/33.3996/60.6507
[16:17:49.816] INFO: roc 10 with ID = 10 has maximal Vcal 57.7571 for pixel 20/10 mean/min/max = 44.8073/31.7977/57.817
[16:17:49.816] INFO: roc 11 with ID = 11 has maximal Vcal 57.5531 for pixel 15/25 mean/min/max = 45.2619/32.9061/57.6177
[16:17:49.816] INFO: roc 12 with ID = 12 has maximal Vcal 59.7027 for pixel 32/6 mean/min/max = 46.8249/33.8196/59.8301
[16:17:49.816] INFO: roc 13 with ID = 13 has maximal Vcal 57.6488 for pixel 50/79 mean/min/max = 45.2078/32.723/57.6926
[16:17:49.817] INFO: roc 14 with ID = 14 has maximal Vcal 60.6185 for pixel 8/3 mean/min/max = 46.7782/32.8436/60.7127
[16:17:49.817] INFO: roc 15 with ID = 15 has maximal Vcal 59.2317 for pixel 1/72 mean/min/max = 46.2893/33.252/59.3267
[16:17:49.817] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:17:49.948] INFO: Expecting 1029120 events.
[16:18:07.170] INFO: 1029120 events read in total (16440ms).
[16:18:07.176] INFO: Expecting 1029120 events.
[16:18:25.529] INFO: 1029120 events read in total (17726ms).
[16:18:25.538] INFO: Expecting 1029120 events.
[16:18:43.975] INFO: 1029120 events read in total (17809ms).
[16:18:43.987] INFO: Expecting 1029120 events.
[16:19:02.313] INFO: 1029120 events read in total (17707ms).
[16:19:02.331] INFO: Expecting 1029120 events.
[16:19:20.665] INFO: 1029120 events read in total (17711ms).
[16:19:20.684] INFO: Expecting 1029120 events.
[16:19:39.056] INFO: 1029120 events read in total (17756ms).
[16:19:39.072] INFO: Expecting 1029120 events.
[16:19:57.482] INFO: 1029120 events read in total (17790ms).
[16:19:57.501] INFO: Expecting 1029120 events.
[16:20:15.787] INFO: 1029120 events read in total (17670ms).
[16:20:15.807] INFO: Expecting 1029120 events.
[16:20:34.182] INFO: 1029120 events read in total (17751ms).
[16:20:34.204] INFO: Expecting 1029120 events.
[16:20:52.562] INFO: 1029120 events read in total (17742ms).
[16:20:52.586] INFO: Expecting 1029120 events.
[16:21:11.024] INFO: 1029120 events read in total (17817ms).
[16:21:11.051] INFO: Expecting 1029120 events.
[16:21:29.516] INFO: 1029120 events read in total (17860ms).
[16:21:29.545] INFO: Expecting 1029120 events.
[16:21:48.056] INFO: 1029120 events read in total (17905ms).
[16:21:48.089] INFO: Expecting 1029120 events.
[16:22:06.500] INFO: 1029120 events read in total (17812ms).
[16:22:06.535] INFO: Expecting 1029120 events.
[16:22:25.040] INFO: 1029120 events read in total (17904ms).
[16:22:25.077] INFO: Expecting 1029120 events.
[16:22:43.456] INFO: 1029120 events read in total (17785ms).
[16:22:43.502] INFO: Test took 293685ms.
[16:22:44.470] INFO: ---> dac: vcal name: TrimThr2 ntrig: 20 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[16:22:44.487] INFO: dacScan split into 1 runs with ntrig = 20
[16:22:44.487] INFO: run 1 of 1
[16:22:44.838] INFO: Expecting 16640000 events.
[16:23:08.252] INFO: 842120 events read in total (22635ms).
[16:23:31.026] INFO: 1683060 events read in total (45409ms).
[16:23:53.782] INFO: 2522200 events read in total (68165ms).
[16:24:16.526] INFO: 3362180 events read in total (90909ms).
[16:24:39.330] INFO: 4202800 events read in total (113713ms).
[16:25:02.032] INFO: 5042200 events read in total (136415ms).
[16:25:24.853] INFO: 5883460 events read in total (159236ms).
[16:25:47.602] INFO: 6724140 events read in total (181985ms).
[16:26:10.371] INFO: 7565740 events read in total (204754ms).
[16:26:33.109] INFO: 8406020 events read in total (227492ms).
[16:26:55.823] INFO: 9240000 events read in total (250206ms).
[16:27:18.588] INFO: 10074680 events read in total (272971ms).
[16:27:41.241] INFO: 10907220 events read in total (295624ms).
[16:28:03.901] INFO: 11739100 events read in total (318284ms).
[16:28:26.449] INFO: 12570260 events read in total (340832ms).
[16:28:48.996] INFO: 13401400 events read in total (363379ms).
[16:29:11.658] INFO: 14231680 events read in total (386041ms).
[16:29:34.263] INFO: 15062460 events read in total (408646ms).
[16:29:56.821] INFO: 15892780 events read in total (431204ms).
[16:30:17.137] INFO: 16640000 events read in total (451520ms).
[16:30:17.208] INFO: Test took 452721ms.
[16:30:17.455] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:30:44.707] INFO: ---> TrimStepCorr4 extremal thresholds: 1.003340 .. 50.766652
[16:30:44.777] INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 20 dacrange: 1 .. 60 (-1/-1) hits flags = 16 (plus default)
[16:30:44.787] INFO: dacScan split into 1 runs with ntrig = 20
[16:30:44.787] INFO: run 1 of 1
[16:30:45.138] INFO: Expecting 4992000 events.
[16:31:09.502] INFO: 1150520 events read in total (23585ms).
[16:31:35.414] INFO: 2300540 events read in total (49497ms).
[16:32:01.311] INFO: 3443860 events read in total (75395ms).
[16:32:27.172] INFO: 4576900 events read in total (101255ms).
[16:32:36.824] INFO: 4992000 events read in total (110907ms).
[16:32:36.846] INFO: Test took 112059ms.
[16:32:36.891] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:32:50.787] INFO: ---> TrimStepCorr2 extremal thresholds: 15.518474 .. 45.453558
[16:32:50.855] INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 20 dacrange: 5 .. 55 (-1/-1) hits flags = 16 (plus default)
[16:32:50.864] INFO: dacScan split into 1 runs with ntrig = 20
[16:32:50.864] INFO: run 1 of 1
[16:32:51.211] INFO: Expecting 4243200 events.
[16:33:17.985] INFO: 1165880 events read in total (25988ms).
[16:33:43.843] INFO: 2331520 events read in total (51846ms).
[16:34:09.742] INFO: 3493200 events read in total (77745ms).
[16:34:26.569] INFO: 4243200 events read in total (94572ms).
[16:34:26.587] INFO: Test took 95722ms.
[16:34:26.624] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:34:39.738] INFO: ---> TrimStepCorr1a extremal thresholds: 19.862803 .. 43.097077
[16:34:39.808] INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 20 dacrange: 9 .. 53 (-1/-1) hits flags = 16 (plus default)
[16:34:39.818] INFO: dacScan split into 1 runs with ntrig = 20
[16:34:39.818] INFO: run 1 of 1
[16:34:40.170] INFO: Expecting 3744000 events.
[16:35:06.943] INFO: 1157900 events read in total (25995ms).
[16:35:31.333] INFO: 2314800 events read in total (50385ms).
[16:35:56.901] INFO: 3469600 events read in total (75953ms).
[16:36:03.476] INFO: 3744000 events read in total (82528ms).
[16:36:03.491] INFO: Test took 83673ms.
[16:36:03.525] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:36:16.224] INFO: ---> TrimStepCorr1b extremal thresholds: 22.478091 .. 42.421988
[16:36:16.293] INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 20 dacrange: 12 .. 52 (-1/-1) hits flags = 16 (plus default)
[16:36:16.303] INFO: dacScan split into 1 runs with ntrig = 20
[16:36:16.303] INFO: run 1 of 1
[16:36:16.652] INFO: Expecting 3411200 events.
[16:36:43.407] INFO: 1145680 events read in total (25976ms).
[16:37:09.462] INFO: 2291020 events read in total (52031ms).
[16:37:35.207] INFO: 3411200 events read in total (77776ms).
[16:37:35.226] INFO: Test took 78924ms.
[16:37:35.263] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:37:48.024] INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[16:37:48.024] INFO: ---> dac: vcal name: TrimThrFinal ntrig: 20 dacrange: 15 .. 55 (-1/-1) hits flags = 16 (plus default)
[16:37:48.034] INFO: dacScan split into 1 runs with ntrig = 20
[16:37:48.034] INFO: run 1 of 1
[16:37:48.383] INFO: Expecting 3411200 events.
[16:38:14.360] INFO: 1074940 events read in total (25198ms).
[16:38:39.754] INFO: 2149880 events read in total (50592ms).
[16:39:03.321] INFO: 3223800 events read in total (74160ms).
[16:39:08.151] INFO: 3411200 events read in total (78989ms).
[16:39:08.171] INFO: Test took 80137ms.
[16:39:08.216] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:39:21.390] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C0.dat
[16:39:21.390] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C1.dat
[16:39:21.390] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C2.dat
[16:39:21.390] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C3.dat
[16:39:21.390] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C4.dat
[16:39:21.390] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C5.dat
[16:39:21.391] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C6.dat
[16:39:21.391] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C7.dat
[16:39:21.391] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C8.dat
[16:39:21.391] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C9.dat
[16:39:21.391] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C10.dat
[16:39:21.391] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C11.dat
[16:39:21.391] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C12.dat
[16:39:21.391] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C13.dat
[16:39:21.391] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C14.dat
[16:39:21.391] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C15.dat
[16:39:21.391] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C0.dat
[16:39:21.397] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C1.dat
[16:39:21.403] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C2.dat
[16:39:21.409] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C3.dat
[16:39:21.414] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C4.dat
[16:39:21.420] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C5.dat
[16:39:21.426] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C6.dat
[16:39:21.432] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C7.dat
[16:39:21.437] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C8.dat
[16:39:21.443] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C9.dat
[16:39:21.449] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C10.dat
[16:39:21.455] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C11.dat
[16:39:21.461] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C12.dat
[16:39:21.466] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C13.dat
[16:39:21.472] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C14.dat
[16:39:21.478] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/trimParameters35_C15.dat
[16:39:21.484] INFO: PixTestTrim::trimTest() done
[16:39:21.484] INFO: vtrim: 97 83 95 92 81 83 86 81 89 90 93 92 100 87 101 89
[16:39:21.484] INFO: vthrcomp: 102 102 97 96 91 101 87 103 89 89 96 91 105 94 92 88
[16:39:21.484] INFO: vcal mean: 34.98 34.94 34.93 34.96 34.98 34.99 35.00 34.95 35.02 34.96 34.96 34.96 35.04 34.95 34.95 34.99
[16:39:21.484] INFO: vcal RMS: 0.74 0.77 0.75 0.72 0.71 0.75 0.71 0.74 0.72 0.73 0.79 0.73 0.72 0.70 0.76 0.70
[16:39:21.484] INFO: bits mean: 9.77 9.84 9.78 9.04 8.77 9.45 9.38 8.37 8.74 8.40 9.68 9.11 8.72 9.16 9.14 8.88
[16:39:21.484] INFO: bits RMS: 2.67 2.67 2.71 2.80 2.74 2.81 2.81 2.95 2.62 2.85 2.71 2.74 2.69 2.77 2.67 2.74
[16:39:21.491] INFO: ----------------------------------------------------------------------
[16:39:21.491] INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[16:39:21.491] INFO: ----------------------------------------------------------------------
[16:39:21.493] INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[16:39:21.503] INFO: dacScan split into 1 runs with ntrig = 10
[16:39:21.503] INFO: run 1 of 1
[16:39:21.850] INFO: Expecting 8320000 events.
[16:39:52.427] INFO: 1203330 events read in total (29799ms).
[16:40:21.934] INFO: 2393420 events read in total (59306ms).
[16:40:51.601] INFO: 3572000 events read in total (88973ms).
[16:41:18.928] INFO: 4737650 events read in total (116300ms).
[16:41:48.307] INFO: 5891540 events read in total (145679ms).
[16:42:17.585] INFO: 7041470 events read in total (174957ms).
[16:42:46.898] INFO: 8193670 events read in total (204270ms).
[16:42:50.429] INFO: 8320000 events read in total (207801ms).
[16:42:50.489] INFO: Test took 208986ms.
[16:42:50.623] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:43:17.836] INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 180 (-1/-1) hits flags = 16 (plus default)
[16:43:17.846] INFO: dacScan split into 1 runs with ntrig = 10
[16:43:17.846] INFO: run 1 of 1
[16:43:18.196] INFO: Expecting 7529600 events.
[16:43:48.939] INFO: 1208680 events read in total (29965ms).
[16:44:18.661] INFO: 2403660 events read in total (59687ms).
[16:44:46.330] INFO: 3589130 events read in total (87356ms).
[16:45:14.384] INFO: 4757350 events read in total (115410ms).
[16:45:43.901] INFO: 5917790 events read in total (144927ms).
[16:46:13.368] INFO: 7076780 events read in total (174394ms).
[16:46:25.043] INFO: 7529600 events read in total (186069ms).
[16:46:25.087] INFO: Test took 187241ms.
[16:46:25.188] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:46:50.442] INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 166 (-1/-1) hits flags = 16 (plus default)
[16:46:50.452] INFO: dacScan split into 1 runs with ntrig = 10
[16:46:50.452] INFO: run 1 of 1
[16:46:50.799] INFO: Expecting 6947200 events.
[16:47:22.094] INFO: 1270580 events read in total (30517ms).
[16:47:52.724] INFO: 2524610 events read in total (61147ms).
[16:48:20.754] INFO: 3761390 events read in total (89177ms).
[16:48:49.387] INFO: 4978350 events read in total (117810ms).
[16:49:19.259] INFO: 6190380 events read in total (147682ms).
[16:49:37.849] INFO: 6947200 events read in total (166272ms).
[16:49:37.885] INFO: Test took 167433ms.
[16:49:37.965] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:50:01.673] INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 166 (-1/-1) hits flags = 16 (plus default)
[16:50:01.686] INFO: dacScan split into 1 runs with ntrig = 10
[16:50:01.686] INFO: run 1 of 1
[16:50:02.037] INFO: Expecting 6947200 events.
[16:50:31.855] INFO: 1269280 events read in total (29039ms).
[16:51:02.239] INFO: 2522090 events read in total (59423ms).
[16:51:32.408] INFO: 3757810 events read in total (89592ms).
[16:52:00.122] INFO: 4973940 events read in total (117306ms).
[16:52:27.860] INFO: 6184710 events read in total (145044ms).
[16:52:46.687] INFO: 6947200 events read in total (163871ms).
[16:52:46.719] INFO: Test took 165033ms.
[16:52:46.802] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:53:10.377] INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 165 (-1/-1) hits flags = 16 (plus default)
[16:53:10.387] INFO: dacScan split into 1 runs with ntrig = 10
[16:53:10.387] INFO: run 1 of 1
[16:53:10.739] INFO: Expecting 6905600 events.
[16:53:40.009] INFO: 1273800 events read in total (28491ms).
[16:54:10.594] INFO: 2531100 events read in total (59076ms).
[16:54:40.899] INFO: 3769420 events read in total (89381ms).
[16:55:08.595] INFO: 4988860 events read in total (117077ms).
[16:55:38.546] INFO: 6203800 events read in total (147028ms).
[16:55:55.838] INFO: 6905600 events read in total (164320ms).
[16:55:55.875] INFO: Test took 165488ms.
[16:55:55.963] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:56:19.339] INFO: PixTestTrim::trimBitTest() done
[16:56:19.340] INFO: PixTestTrim::doTest() done, duration: 2955 seconds
[16:56:20.004] INFO: ######################################################################
[16:56:20.004] INFO: PixTestPhOptimization::doTest() Ntrig = 16
[16:56:20.004] INFO: ######################################################################
[16:56:20.352] INFO: Expecting 41600 events.
[16:56:24.401] INFO: 41600 events read in total (3270ms).
[16:56:24.401] INFO: Test took 4395ms.
[16:56:24.412] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:56:25.176] INFO: Expecting 41600 events.
[16:56:29.351] INFO: 41600 events read in total (3397ms).
[16:56:29.351] INFO: Test took 4528ms.
[16:56:29.357] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:56:29.856] INFO: Expecting 41600 events.
[16:56:34.028] INFO: 41600 events read in total (3393ms).
[16:56:34.028] INFO: Test took 4559ms.
[16:56:34.038] INFO: Fetched DAQ statistics. Counters are being reset now.
[16:56:34.049] INFO: The DUT currently contains the following objects:
[16:56:34.049] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:34.049] INFO: TBM Core alpha (0): 7 registers set
[16:56:34.049] INFO: TBM Core beta (1): 7 registers set
[16:56:34.049] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:34.049] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.049] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:34.530] INFO: Expecting 2560 events.
[16:56:35.557] INFO: 2560 events read in total (249ms).
[16:56:35.558] INFO: Test took 1509ms.
[16:56:35.558] INFO: The DUT currently contains the following objects:
[16:56:35.558] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:35.558] INFO: TBM Core alpha (0): 7 registers set
[16:56:35.558] INFO: TBM Core beta (1): 7 registers set
[16:56:35.558] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:35.558] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.558] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.558] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.558] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.558] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.558] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.559] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.559] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.559] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.559] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.559] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.559] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.559] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.559] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.559] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:35.559] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:36.129] INFO: Expecting 2560 events.
[16:56:37.157] INFO: 2560 events read in total (249ms).
[16:56:37.157] INFO: Test took 1598ms.
[16:56:37.157] INFO: The DUT currently contains the following objects:
[16:56:37.157] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:37.157] INFO: TBM Core alpha (0): 7 registers set
[16:56:37.157] INFO: TBM Core beta (1): 7 registers set
[16:56:37.157] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:37.157] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.157] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.157] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.157] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.157] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.157] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.158] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.158] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.158] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.158] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.158] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.158] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.158] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.158] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.158] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.158] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:37.728] INFO: Expecting 2560 events.
[16:56:38.755] INFO: 2560 events read in total (248ms).
[16:56:38.756] INFO: Test took 1598ms.
[16:56:38.756] INFO: The DUT currently contains the following objects:
[16:56:38.756] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:38.756] INFO: TBM Core alpha (0): 7 registers set
[16:56:38.756] INFO: TBM Core beta (1): 7 registers set
[16:56:38.756] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:38.756] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.756] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.756] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.756] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.756] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.756] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.756] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.756] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.756] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.757] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.757] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.757] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.757] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.757] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.757] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:38.757] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:39.327] INFO: Expecting 2560 events.
[16:56:40.354] INFO: 2560 events read in total (248ms).
[16:56:40.354] INFO: Test took 1597ms.
[16:56:40.355] INFO: The DUT currently contains the following objects:
[16:56:40.355] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:40.355] INFO: TBM Core alpha (0): 7 registers set
[16:56:40.355] INFO: TBM Core beta (1): 7 registers set
[16:56:40.355] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:40.355] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.355] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:40.926] INFO: Expecting 2560 events.
[16:56:41.949] INFO: 2560 events read in total (245ms).
[16:56:41.949] INFO: Test took 1594ms.
[16:56:41.949] INFO: The DUT currently contains the following objects:
[16:56:41.949] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:41.949] INFO: TBM Core alpha (0): 7 registers set
[16:56:41.949] INFO: TBM Core beta (1): 7 registers set
[16:56:41.949] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:41.949] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.949] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:41.950] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:42.521] INFO: Expecting 2560 events.
[16:56:43.548] INFO: 2560 events read in total (248ms).
[16:56:43.549] INFO: Test took 1599ms.
[16:56:43.549] INFO: The DUT currently contains the following objects:
[16:56:43.549] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:43.549] INFO: TBM Core alpha (0): 7 registers set
[16:56:43.549] INFO: TBM Core beta (1): 7 registers set
[16:56:43.549] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:43.549] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.549] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.549] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.549] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.549] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.549] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.549] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.549] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.549] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.549] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.549] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.549] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.550] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.550] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.550] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:43.550] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:44.120] INFO: Expecting 2560 events.
[16:56:45.145] INFO: 2560 events read in total (246ms).
[16:56:45.145] INFO: Test took 1595ms.
[16:56:45.146] INFO: The DUT currently contains the following objects:
[16:56:45.146] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:45.146] INFO: TBM Core alpha (0): 7 registers set
[16:56:45.146] INFO: TBM Core beta (1): 7 registers set
[16:56:45.146] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:45.146] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.146] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:45.718] INFO: Expecting 2560 events.
[16:56:46.741] INFO: 2560 events read in total (245ms).
[16:56:46.741] INFO: Test took 1595ms.
[16:56:46.741] INFO: The DUT currently contains the following objects:
[16:56:46.741] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:46.741] INFO: TBM Core alpha (0): 7 registers set
[16:56:46.741] INFO: TBM Core beta (1): 7 registers set
[16:56:46.741] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:46.741] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:46.741] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:47.312] INFO: Expecting 2560 events.
[16:56:48.333] INFO: 2560 events read in total (242ms).
[16:56:48.334] INFO: Test took 1593ms.
[16:56:48.334] INFO: The DUT currently contains the following objects:
[16:56:48.334] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:48.334] INFO: TBM Core alpha (0): 7 registers set
[16:56:48.334] INFO: TBM Core beta (1): 7 registers set
[16:56:48.334] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:48.334] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.334] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:48.905] INFO: Expecting 2560 events.
[16:56:49.926] INFO: 2560 events read in total (243ms).
[16:56:49.926] INFO: Test took 1592ms.
[16:56:49.927] INFO: The DUT currently contains the following objects:
[16:56:49.927] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:49.927] INFO: TBM Core alpha (0): 7 registers set
[16:56:49.927] INFO: TBM Core beta (1): 7 registers set
[16:56:49.927] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:49.927] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:49.927] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:50.498] INFO: Expecting 2560 events.
[16:56:51.519] INFO: 2560 events read in total (243ms).
[16:56:51.520] INFO: Test took 1593ms.
[16:56:51.520] INFO: The DUT currently contains the following objects:
[16:56:51.520] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:51.520] INFO: TBM Core alpha (0): 7 registers set
[16:56:51.520] INFO: TBM Core beta (1): 7 registers set
[16:56:51.520] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:51.520] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:51.520] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:52.091] INFO: Expecting 2560 events.
[16:56:53.112] INFO: 2560 events read in total (242ms).
[16:56:53.112] INFO: Test took 1592ms.
[16:56:53.112] INFO: The DUT currently contains the following objects:
[16:56:53.112] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:53.112] INFO: TBM Core alpha (0): 7 registers set
[16:56:53.112] INFO: TBM Core beta (1): 7 registers set
[16:56:53.112] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:53.112] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.112] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:53.683] INFO: Expecting 2560 events.
[16:56:54.705] INFO: 2560 events read in total (243ms).
[16:56:54.705] INFO: Test took 1593ms.
[16:56:54.706] INFO: The DUT currently contains the following objects:
[16:56:54.706] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:54.706] INFO: TBM Core alpha (0): 7 registers set
[16:56:54.706] INFO: TBM Core beta (1): 7 registers set
[16:56:54.706] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:54.706] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:54.706] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:55.277] INFO: Expecting 2560 events.
[16:56:56.298] INFO: 2560 events read in total (243ms).
[16:56:56.298] INFO: Test took 1592ms.
[16:56:56.299] INFO: The DUT currently contains the following objects:
[16:56:56.299] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:56.299] INFO: TBM Core alpha (0): 7 registers set
[16:56:56.299] INFO: TBM Core beta (1): 7 registers set
[16:56:56.299] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:56.299] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.299] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:56.870] INFO: Expecting 2560 events.
[16:56:57.892] INFO: 2560 events read in total (244ms).
[16:56:57.892] INFO: Test took 1593ms.
[16:56:57.892] INFO: The DUT currently contains the following objects:
[16:56:57.892] INFO: 2 TBM Cores tbm08c (2 ON)
[16:56:57.892] INFO: TBM Core alpha (0): 7 registers set
[16:56:57.892] INFO: TBM Core beta (1): 7 registers set
[16:56:57.892] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[16:56:57.892] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.892] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:57.893] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[16:56:58.463] INFO: Expecting 2560 events.
[16:56:59.486] INFO: 2560 events read in total (244ms).
[16:56:59.486] INFO: Test took 1593ms.
[16:56:59.489] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[16:57:00.060] INFO: Expecting 655360 events.
[16:57:12.104] INFO: 655360 events read in total (11266ms).
[16:57:12.118] INFO: Expecting 655360 events.
[16:57:24.838] INFO: 655360 events read in total (12148ms).
[16:57:24.856] INFO: Expecting 655360 events.
[16:57:37.665] INFO: 655360 events read in total (12236ms).
[16:57:37.688] INFO: Expecting 655360 events.
[16:57:50.477] INFO: 655360 events read in total (12225ms).
[16:57:50.501] INFO: Expecting 655360 events.
[16:58:02.915] INFO: 655360 events read in total (11852ms).
[16:58:02.942] INFO: Expecting 655360 events.
[16:58:14.852] INFO: 655360 events read in total (11341ms).
[16:58:14.888] INFO: Expecting 655360 events.
[16:58:27.031] INFO: 655360 events read in total (11586ms).
[16:58:27.066] INFO: Expecting 655360 events.
[16:58:39.773] INFO: 655360 events read in total (12153ms).
[16:58:39.816] INFO: Expecting 655360 events.
[16:58:52.711] INFO: 655360 events read in total (12347ms).
[16:58:52.762] INFO: Expecting 655360 events.
[16:59:05.546] INFO: 655360 events read in total (12247ms).
[16:59:05.594] INFO: Expecting 655360 events.
[16:59:18.531] INFO: 655360 events read in total (12398ms).
[16:59:18.588] INFO: Expecting 655360 events.
[16:59:31.341] INFO: 655360 events read in total (12219ms).
[16:59:31.398] INFO: Expecting 655360 events.
[16:59:43.512] INFO: 655360 events read in total (11587ms).
[16:59:43.574] INFO: Expecting 655360 events.
[16:59:55.482] INFO: 655360 events read in total (11373ms).
[16:59:55.548] INFO: Expecting 655360 events.
[17:00:07.683] INFO: 655360 events read in total (11603ms).
[17:00:07.750] INFO: Expecting 655360 events.
[17:00:20.582] INFO: 655360 events read in total (12305ms).
[17:00:20.662] INFO: Test took 201173ms.
[17:00:20.764] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:00:21.134] INFO: Expecting 655360 events.
[17:00:34.124] INFO: 655360 events read in total (12211ms).
[17:00:34.135] INFO: Expecting 655360 events.
[17:00:46.903] INFO: 655360 events read in total (12195ms).
[17:00:46.922] INFO: Expecting 655360 events.
[17:00:59.688] INFO: 655360 events read in total (12192ms).
[17:00:59.708] INFO: Expecting 655360 events.
[17:01:12.401] INFO: 655360 events read in total (12116ms).
[17:01:12.425] INFO: Expecting 655360 events.
[17:01:24.243] INFO: 655360 events read in total (11247ms).
[17:01:24.273] INFO: Expecting 655360 events.
[17:01:36.121] INFO: 655360 events read in total (11281ms).
[17:01:36.152] INFO: Expecting 655360 events.
[17:01:48.824] INFO: 655360 events read in total (12103ms).
[17:01:48.861] INFO: Expecting 655360 events.
[17:02:01.573] INFO: 655360 events read in total (12146ms).
[17:02:01.615] INFO: Expecting 655360 events.
[17:02:14.436] INFO: 655360 events read in total (12265ms).
[17:02:14.480] INFO: Expecting 655360 events.
[17:02:27.296] INFO: 655360 events read in total (12262ms).
[17:02:27.344] INFO: Expecting 655360 events.
[17:02:40.110] INFO: 655360 events read in total (12216ms).
[17:02:40.164] INFO: Expecting 655360 events.
[17:02:52.855] INFO: 655360 events read in total (12157ms).
[17:02:52.917] INFO: Expecting 655360 events.
[17:03:05.670] INFO: 655360 events read in total (12222ms).
[17:03:05.731] INFO: Expecting 655360 events.
[17:03:18.521] INFO: 655360 events read in total (12251ms).
[17:03:18.588] INFO: Expecting 655360 events.
[17:03:30.398] INFO: 655360 events read in total (11280ms).
[17:03:30.467] INFO: Expecting 655360 events.
[17:03:42.333] INFO: 655360 events read in total (11325ms).
[17:03:42.405] INFO: Test took 201641ms.
[17:03:42.592] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.598] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.604] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.611] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.617] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.623] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.630] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.636] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.642] INFO: safety margin for low PH: adding 1, margin is now 21
[17:03:42.649] INFO: safety margin for low PH: adding 2, margin is now 22
[17:03:42.655] INFO: safety margin for low PH: adding 3, margin is now 23
[17:03:42.661] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.668] INFO: safety margin for low PH: adding 1, margin is now 21
[17:03:42.674] INFO: safety margin for low PH: adding 2, margin is now 22
[17:03:42.680] INFO: safety margin for low PH: adding 3, margin is now 23
[17:03:42.686] INFO: safety margin for low PH: adding 4, margin is now 24
[17:03:42.693] INFO: safety margin for low PH: adding 5, margin is now 25
[17:03:42.699] INFO: safety margin for low PH: adding 6, margin is now 26
[17:03:42.705] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.712] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.718] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.724] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.731] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.737] INFO: safety margin for low PH: adding 1, margin is now 21
[17:03:42.743] INFO: safety margin for low PH: adding 2, margin is now 22
[17:03:42.750] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.756] INFO: safety margin for low PH: adding 0, margin is now 20
[17:03:42.790] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C0.dat
[17:03:42.790] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C1.dat
[17:03:42.790] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C2.dat
[17:03:42.790] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C3.dat
[17:03:42.790] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C4.dat
[17:03:42.790] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C5.dat
[17:03:42.790] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C6.dat
[17:03:42.790] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C7.dat
[17:03:42.790] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C8.dat
[17:03:42.791] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C9.dat
[17:03:42.791] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C10.dat
[17:03:42.791] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C11.dat
[17:03:42.791] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C12.dat
[17:03:42.791] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C13.dat
[17:03:42.791] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C14.dat
[17:03:42.791] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/dacParameters35_C15.dat
[17:03:43.141] INFO: Expecting 41600 events.
[17:03:47.197] INFO: 41600 events read in total (3277ms).
[17:03:47.198] INFO: Test took 4405ms.
[17:03:47.935] INFO: Expecting 41600 events.
[17:03:52.082] INFO: 41600 events read in total (3369ms).
[17:03:52.083] INFO: Test took 4496ms.
[17:03:52.827] INFO: Expecting 41600 events.
[17:03:57.012] INFO: 41600 events read in total (3406ms).
[17:03:57.013] INFO: Test took 4545ms.
[17:03:57.398] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:03:57.530] INFO: Expecting 2560 events.
[17:03:58.557] INFO: 2560 events read in total (249ms).
[17:03:58.557] INFO: Test took 1159ms.
[17:03:58.559] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:03:59.131] INFO: Expecting 2560 events.
[17:04:00.158] INFO: 2560 events read in total (249ms).
[17:04:00.158] INFO: Test took 1599ms.
[17:04:00.160] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:00.731] INFO: Expecting 2560 events.
[17:04:01.758] INFO: 2560 events read in total (248ms).
[17:04:01.758] INFO: Test took 1598ms.
[17:04:01.761] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:02.331] INFO: Expecting 2560 events.
[17:04:03.357] INFO: 2560 events read in total (247ms).
[17:04:03.358] INFO: Test took 1597ms.
[17:04:03.360] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:03.930] INFO: Expecting 2560 events.
[17:04:04.957] INFO: 2560 events read in total (248ms).
[17:04:04.957] INFO: Test took 1597ms.
[17:04:04.959] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:05.530] INFO: Expecting 2560 events.
[17:04:06.557] INFO: 2560 events read in total (249ms).
[17:04:06.557] INFO: Test took 1598ms.
[17:04:06.559] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:07.130] INFO: Expecting 2560 events.
[17:04:08.156] INFO: 2560 events read in total (247ms).
[17:04:08.156] INFO: Test took 1597ms.
[17:04:08.158] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:08.729] INFO: Expecting 2560 events.
[17:04:09.755] INFO: 2560 events read in total (248ms).
[17:04:09.756] INFO: Test took 1598ms.
[17:04:09.758] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:10.328] INFO: Expecting 2560 events.
[17:04:11.354] INFO: 2560 events read in total (247ms).
[17:04:11.358] INFO: Test took 1600ms.
[17:04:11.361] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:11.928] INFO: Expecting 2560 events.
[17:04:12.955] INFO: 2560 events read in total (249ms).
[17:04:12.955] INFO: Test took 1595ms.
[17:04:12.958] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:13.528] INFO: Expecting 2560 events.
[17:04:14.554] INFO: 2560 events read in total (248ms).
[17:04:14.555] INFO: Test took 1598ms.
[17:04:14.557] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:15.127] INFO: Expecting 2560 events.
[17:04:16.153] INFO: 2560 events read in total (247ms).
[17:04:16.153] INFO: Test took 1596ms.
[17:04:16.155] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:16.725] INFO: Expecting 2560 events.
[17:04:17.751] INFO: 2560 events read in total (247ms).
[17:04:17.752] INFO: Test took 1597ms.
[17:04:17.754] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:18.325] INFO: Expecting 2560 events.
[17:04:19.354] INFO: 2560 events read in total (250ms).
[17:04:19.354] INFO: Test took 1600ms.
[17:04:19.357] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:19.926] INFO: Expecting 2560 events.
[17:04:20.952] INFO: 2560 events read in total (247ms).
[17:04:20.953] INFO: Test took 1597ms.
[17:04:20.955] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:21.525] INFO: Expecting 2560 events.
[17:04:22.550] INFO: 2560 events read in total (247ms).
[17:04:22.551] INFO: Test took 1596ms.
[17:04:22.553] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:23.123] INFO: Expecting 2560 events.
[17:04:24.150] INFO: 2560 events read in total (248ms).
[17:04:24.151] INFO: Test took 1598ms.
[17:04:24.153] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:24.723] INFO: Expecting 2560 events.
[17:04:25.750] INFO: 2560 events read in total (248ms).
[17:04:25.751] INFO: Test took 1598ms.
[17:04:25.753] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:26.323] INFO: Expecting 2560 events.
[17:04:27.349] INFO: 2560 events read in total (247ms).
[17:04:27.350] INFO: Test took 1597ms.
[17:04:27.352] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:27.922] INFO: Expecting 2560 events.
[17:04:28.949] INFO: 2560 events read in total (248ms).
[17:04:28.949] INFO: Test took 1597ms.
[17:04:28.951] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:29.522] INFO: Expecting 2560 events.
[17:04:30.548] INFO: 2560 events read in total (248ms).
[17:04:30.548] INFO: Test took 1597ms.
[17:04:30.550] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:31.121] INFO: Expecting 2560 events.
[17:04:32.148] INFO: 2560 events read in total (249ms).
[17:04:32.148] INFO: Test took 1598ms.
[17:04:32.151] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:32.721] INFO: Expecting 2560 events.
[17:04:33.745] INFO: 2560 events read in total (246ms).
[17:04:33.746] INFO: Test took 1596ms.
[17:04:33.748] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:34.318] INFO: Expecting 2560 events.
[17:04:35.345] INFO: 2560 events read in total (249ms).
[17:04:35.345] INFO: Test took 1597ms.
[17:04:35.347] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:35.917] INFO: Expecting 2560 events.
[17:04:36.944] INFO: 2560 events read in total (248ms).
[17:04:36.944] INFO: Test took 1597ms.
[17:04:36.947] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:37.516] INFO: Expecting 2560 events.
[17:04:38.540] INFO: 2560 events read in total (245ms).
[17:04:38.541] INFO: Test took 1595ms.
[17:04:38.543] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:39.113] INFO: Expecting 2560 events.
[17:04:40.138] INFO: 2560 events read in total (246ms).
[17:04:40.139] INFO: Test took 1596ms.
[17:04:40.141] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:40.712] INFO: Expecting 2560 events.
[17:04:41.738] INFO: 2560 events read in total (248ms).
[17:04:41.739] INFO: Test took 1598ms.
[17:04:41.741] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:42.311] INFO: Expecting 2560 events.
[17:04:43.338] INFO: 2560 events read in total (248ms).
[17:04:43.338] INFO: Test took 1597ms.
[17:04:43.341] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:43.911] INFO: Expecting 2560 events.
[17:04:44.938] INFO: 2560 events read in total (248ms).
[17:04:44.938] INFO: Test took 1597ms.
[17:04:44.941] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:45.511] INFO: Expecting 2560 events.
[17:04:46.538] INFO: 2560 events read in total (249ms).
[17:04:46.539] INFO: Test took 1599ms.
[17:04:46.541] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[17:04:47.111] INFO: Expecting 2560 events.
[17:04:48.138] INFO: 2560 events read in total (248ms).
[17:04:48.139] INFO: Test took 1598ms.
[17:04:48.910] INFO: PixTestPhOptimization::doTest() done, duration: 508 seconds
[17:04:48.910] INFO: PH scale (per ROC): 80 65 79 70 69 74 79 73 75 61 70 82 72 69 76 68
[17:04:48.910] INFO: PH offset (per ROC): 170 163 172 184 173 189 165 176 176 167 160 170 189 174 174 175
[17:04:49.085] INFO: ######################################################################
[17:04:49.085] INFO: PixTestGainPedestal::fullTest() ntrig = 1
[17:04:49.085] INFO: ######################################################################
[17:04:49.097] INFO: scanning low vcal = 10
[17:04:49.446] INFO: Expecting 4160 events.
[17:04:52.320] INFO: 4160 events read in total (2095ms).
[17:04:52.320] INFO: Test took 3223ms.
[17:04:52.322] INFO: scanning low vcal = 20
[17:04:52.893] INFO: Expecting 4160 events.
[17:04:55.765] INFO: 4160 events read in total (2093ms).
[17:04:55.766] INFO: Test took 3444ms.
[17:04:55.768] INFO: scanning low vcal = 30
[17:04:56.338] INFO: Expecting 4160 events.
[17:04:59.217] INFO: 4160 events read in total (2100ms).
[17:04:59.217] INFO: Test took 3449ms.
[17:04:59.219] INFO: scanning low vcal = 40
[17:04:59.787] INFO: Expecting 4160 events.
[17:05:02.727] INFO: 4160 events read in total (2161ms).
[17:05:02.728] INFO: Test took 3509ms.
[17:05:02.730] INFO: scanning low vcal = 50
[17:05:03.278] INFO: Expecting 4160 events.
[17:05:06.223] INFO: 4160 events read in total (2167ms).
[17:05:06.223] INFO: Test took 3493ms.
[17:05:06.226] INFO: scanning low vcal = 60
[17:05:06.772] INFO: Expecting 4160 events.
[17:05:09.712] INFO: 4160 events read in total (2161ms).
[17:05:09.712] INFO: Test took 3486ms.
[17:05:09.715] INFO: scanning low vcal = 70
[17:05:10.259] INFO: Expecting 4160 events.
[17:05:13.213] INFO: 4160 events read in total (2175ms).
[17:05:13.214] INFO: Test took 3499ms.
[17:05:13.218] INFO: scanning low vcal = 80
[17:05:13.759] INFO: Expecting 4160 events.
[17:05:16.713] INFO: 4160 events read in total (2175ms).
[17:05:16.714] INFO: Test took 3496ms.
[17:05:16.717] INFO: scanning low vcal = 90
[17:05:17.259] INFO: Expecting 4160 events.
[17:05:20.286] INFO: 4160 events read in total (2248ms).
[17:05:20.287] INFO: Test took 3570ms.
[17:05:20.290] INFO: scanning low vcal = 100
[17:05:20.836] INFO: Expecting 4160 events.
[17:05:23.782] INFO: 4160 events read in total (2168ms).
[17:05:23.783] INFO: Test took 3493ms.
[17:05:23.786] INFO: scanning low vcal = 110
[17:05:24.328] INFO: Expecting 4160 events.
[17:05:27.271] INFO: 4160 events read in total (2164ms).
[17:05:27.272] INFO: Test took 3486ms.
[17:05:27.274] INFO: scanning low vcal = 120
[17:05:27.822] INFO: Expecting 4160 events.
[17:05:30.763] INFO: 4160 events read in total (2163ms).
[17:05:30.763] INFO: Test took 3489ms.
[17:05:30.766] INFO: scanning low vcal = 130
[17:05:31.313] INFO: Expecting 4160 events.
[17:05:34.262] INFO: 4160 events read in total (2170ms).
[17:05:34.262] INFO: Test took 3496ms.
[17:05:34.265] INFO: scanning low vcal = 140
[17:05:34.806] INFO: Expecting 4160 events.
[17:05:37.749] INFO: 4160 events read in total (2164ms).
[17:05:37.749] INFO: Test took 3484ms.
[17:05:37.752] INFO: scanning low vcal = 150
[17:05:38.300] INFO: Expecting 4160 events.
[17:05:41.246] INFO: 4160 events read in total (2168ms).
[17:05:41.247] INFO: Test took 3495ms.
[17:05:41.249] INFO: scanning low vcal = 160
[17:05:41.792] INFO: Expecting 4160 events.
[17:05:44.737] INFO: 4160 events read in total (2166ms).
[17:05:44.737] INFO: Test took 3487ms.
[17:05:44.740] INFO: scanning low vcal = 170
[17:05:45.282] INFO: Expecting 4160 events.
[17:05:48.230] INFO: 4160 events read in total (2169ms).
[17:05:48.231] INFO: Test took 3491ms.
[17:05:48.235] INFO: scanning low vcal = 180
[17:05:48.775] INFO: Expecting 4160 events.
[17:05:51.722] INFO: 4160 events read in total (2169ms).
[17:05:51.722] INFO: Test took 3487ms.
[17:05:51.725] INFO: scanning low vcal = 190
[17:05:52.267] INFO: Expecting 4160 events.
[17:05:55.215] INFO: 4160 events read in total (2170ms).
[17:05:55.215] INFO: Test took 3490ms.
[17:05:55.218] INFO: scanning low vcal = 200
[17:05:55.760] INFO: Expecting 4160 events.
[17:05:58.692] INFO: 4160 events read in total (2153ms).
[17:05:58.693] INFO: Test took 3475ms.
[17:05:58.696] INFO: scanning low vcal = 210
[17:05:59.241] INFO: Expecting 4160 events.
[17:06:02.186] INFO: 4160 events read in total (2166ms).
[17:06:02.187] INFO: Test took 3491ms.
[17:06:02.190] INFO: scanning low vcal = 220
[17:06:02.731] INFO: Expecting 4160 events.
[17:06:05.677] INFO: 4160 events read in total (2168ms).
[17:06:05.678] INFO: Test took 3488ms.
[17:06:05.680] INFO: scanning low vcal = 230
[17:06:06.222] INFO: Expecting 4160 events.
[17:06:09.169] INFO: 4160 events read in total (2168ms).
[17:06:09.169] INFO: Test took 3488ms.
[17:06:09.173] INFO: scanning low vcal = 240
[17:06:09.714] INFO: Expecting 4160 events.
[17:06:12.662] INFO: 4160 events read in total (2169ms).
[17:06:12.663] INFO: Test took 3490ms.
[17:06:12.665] INFO: scanning low vcal = 250
[17:06:13.208] INFO: Expecting 4160 events.
[17:06:16.149] INFO: 4160 events read in total (2163ms).
[17:06:16.150] INFO: Test took 3485ms.
[17:06:16.155] INFO: scanning high vcal = 30 (= 210 in low range)
[17:06:16.702] INFO: Expecting 4160 events.
[17:06:19.648] INFO: 4160 events read in total (2167ms).
[17:06:19.648] INFO: Test took 3493ms.
[17:06:19.651] INFO: scanning high vcal = 50 (= 350 in low range)
[17:06:20.194] INFO: Expecting 4160 events.
[17:06:23.140] INFO: 4160 events read in total (2167ms).
[17:06:23.140] INFO: Test took 3489ms.
[17:06:23.143] INFO: scanning high vcal = 70 (= 490 in low range)
[17:06:23.687] INFO: Expecting 4160 events.
[17:06:26.642] INFO: 4160 events read in total (2177ms).
[17:06:26.643] INFO: Test took 3500ms.
[17:06:26.646] INFO: scanning high vcal = 90 (= 630 in low range)
[17:06:27.190] INFO: Expecting 4160 events.
[17:06:30.215] INFO: 4160 events read in total (2246ms).
[17:06:30.216] INFO: Test took 3570ms.
[17:06:30.219] INFO: scanning high vcal = 200 (= 1400 in low range)
[17:06:30.757] INFO: Expecting 4160 events.
[17:06:33.692] INFO: 4160 events read in total (2156ms).
[17:06:33.693] INFO: Test took 3474ms.
[17:06:34.189] INFO: PixTestGainPedestal::measure() done
[17:07:07.951] INFO: PixTestGainPedestal::fit() done
[17:07:07.951] INFO: non-linearity mean: 0.953 0.951 0.954 0.953 0.951 0.959 0.951 0.959 0.961 0.955 0.952 0.958 0.960 0.952 0.952 0.954
[17:07:07.951] INFO: non-linearity RMS: 0.006 0.006 0.007 0.007 0.008 0.006 0.007 0.006 0.004 0.008 0.008 0.007 0.006 0.006 0.008 0.008
[17:07:07.951] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C0.dat
[17:07:07.970] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C1.dat
[17:07:07.989] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C2.dat
[17:07:08.008] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C3.dat
[17:07:08.027] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C4.dat
[17:07:08.046] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C5.dat
[17:07:08.065] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C6.dat
[17:07:08.084] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C7.dat
[17:07:08.102] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C8.dat
[17:07:08.121] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C9.dat
[17:07:08.139] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C10.dat
[17:07:08.158] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C11.dat
[17:07:08.177] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C12.dat
[17:07:08.196] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C13.dat
[17:07:08.214] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C14.dat
[17:07:08.233] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/phCalibrationFitErr35_C15.dat
[17:07:08.251] INFO: PixTestGainPedestal::doTest() done, duration: 139 seconds
[17:07:08.258] INFO: readReadbackCal: M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C0.dat .. M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C15.dat
[17:07:08.267] INFO: PixTestReadback::doTest() start.
[17:07:08.268] INFO: PixTestReadback::RES sent once
[17:07:20.788] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C0.dat
[17:07:20.788] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C1.dat
[17:07:20.788] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C2.dat
[17:07:20.788] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C3.dat
[17:07:20.788] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C4.dat
[17:07:20.788] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C5.dat
[17:07:20.789] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C6.dat
[17:07:20.789] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C7.dat
[17:07:20.789] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C8.dat
[17:07:20.789] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C9.dat
[17:07:20.789] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C10.dat
[17:07:20.789] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C11.dat
[17:07:20.789] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C12.dat
[17:07:20.789] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C13.dat
[17:07:20.789] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C14.dat
[17:07:20.789] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C15.dat
[17:07:20.813] INFO: PixTestPattern:: pg_setup set to default.
[17:07:20.813] INFO: PixTestReadback::RES sent once
[17:07:33.312] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C0.dat
[17:07:33.312] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C1.dat
[17:07:33.312] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C2.dat
[17:07:33.312] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C3.dat
[17:07:33.312] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C4.dat
[17:07:33.313] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C5.dat
[17:07:33.313] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C6.dat
[17:07:33.313] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C7.dat
[17:07:33.313] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C8.dat
[17:07:33.313] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C9.dat
[17:07:33.313] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C10.dat
[17:07:33.313] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C11.dat
[17:07:33.313] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C12.dat
[17:07:33.313] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C13.dat
[17:07:33.313] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C14.dat
[17:07:33.313] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C15.dat
[17:07:33.341] INFO: PixTestPattern:: pg_setup set to default.
[17:07:33.342] INFO: PixTestReadback::RES sent once
[17:07:42.983] INFO: PixTestPattern:: pg_setup set to default.
[17:07:42.983] INFO: Vbg will be calibrated using Vd calibration
[17:07:42.983] INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 157.2calibrated Vbg = 1.2445 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 150.8calibrated Vbg = 1.2363 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158.2calibrated Vbg = 1.23998 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 154calibrated Vbg = 1.24563 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 149.6calibrated Vbg = 1.25372 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 150.4calibrated Vbg = 1.25335 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 148.8calibrated Vbg = 1.25444 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 155.4calibrated Vbg = 1.25436 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 154.7calibrated Vbg = 1.25448 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 150.8calibrated Vbg = 1.25405 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 150.8calibrated Vbg = 1.24664 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 145.4calibrated Vbg = 1.24451 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 144.6calibrated Vbg = 1.24372 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 153.5calibrated Vbg = 1.2442 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 153.4calibrated Vbg = 1.24247 :::*/*/*/*/
[17:07:42.983] INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 150.4calibrated Vbg = 1.24281 :::*/*/*/*/
[17:07:42.986] INFO: PixTestReadback::RES sent once
[17:10:52.784] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C0.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C1.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C2.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C3.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C4.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C5.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C6.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C7.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C8.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C9.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C10.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C11.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C12.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C13.dat
[17:10:52.785] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C14.dat
[17:10:52.786] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/004_Fulltest_p17/readbackCal_C15.dat
[17:10:52.819] INFO: PixTestPattern:: pg_setup set to default.
[17:10:52.820] INFO: PixTestReadback::doTest() done
[17:10:52.837] INFO: enter test to run
[17:10:52.838] INFO: test: BB2 no parameter change
[17:10:52.838] INFO: running: bb2
[17:10:52.839] INFO: ######################################################################
[17:10:52.839] INFO: PixTestBB2Map::doTest() Ntrig = 16, VcalS = 255, PlWidth = 35
[17:10:52.839] INFO: ######################################################################
[17:10:52.841] INFO: ----------------------------------------------------------------------
[17:10:52.841] INFO: PixTestBB2Map::setVana() target Ia = 30 mA/ROC
[17:10:52.841] INFO: ----------------------------------------------------------------------
[17:11:12.402] INFO: PixTestBB2Map::setVana() done, Module Ia 468.7 mA = 29.2937 mA/ROC
[17:11:12.403] INFO: ----------------------------------------------------------------------
[17:11:12.403] INFO: PixTestBB2Map::setVthrCompCalDel()
[17:11:12.403] INFO: ----------------------------------------------------------------------
[17:11:12.544] INFO: Expecting 1048576 events.
[17:11:23.752] ERROR: <datapipe.cc/CheckEventValidity:L480> Channel 0 Number of ROCs (1) != Token Chain Length (8)
[17:11:23.755] ERROR: <datapipe.cc/CheckEventID:L453> Channel 0 Event ID mismatch: local ID (21) != TBM ID (130)
[17:11:33.600] INFO: 1048576 events read in total (20278ms).
[17:11:33.605] INFO: Test took 21197ms.
[17:11:34.039] INFO: PixTestBB2Map::setVthrCompCalDel() done
[17:11:34.039] INFO: CalDel: 111 110 134 130 133 117 124 106 126 120 112 121 139 140 139 114
[17:11:34.039] INFO: VthrComp: 123 126 121 119 112 120 107 119 100 107 108 101 120 118 109 97
[17:11:34.409] INFO: Expecting 8519680 events.
[17:12:02.858] INFO: 1348480 events read in total (27670ms).
[17:12:30.094] INFO: 2683120 events read in total (54907ms).
[17:12:59.198] INFO: 3998688 events read in total (84010ms).
[17:13:28.191] INFO: 5314160 events read in total (113003ms).
[17:13:57.207] INFO: 6638032 events read in total (142019ms).
[17:14:26.272] INFO: 7971360 events read in total (171084ms).
[17:14:38.385] INFO: 8519680 events read in total (183197ms).
[17:14:38.412] INFO: Test took 184352ms.
[17:14:39.049] INFO: Missing Bumps: 0 0 0 0 2 0 0 2 0 0 0 0 2 0 0 72
[17:14:39.049] INFO: Separation Cut: 32.01 42.09 40.35 41.66 38.07 39.07 34.69 35.64 25.70 31.55 40.28 31.49 45.00 31.53 36.65 45.00
[17:14:39.049] INFO: PixTestBB2Map::doTest() done,226 seconds
[17:14:39.364] INFO: enter test to run
[17:14:39.364] INFO: test: q no parameter change
[17:14:40.006] QUIET: Connection to board 85 closed.
[17:14:40.017] INFO: pXar: this is the end, my friend