[11:32:53.878] INFO: === Welcome to pxar ===
[11:32:53.878] INFO: === Today: 2015/09/10
[11:32:53.878] INFO: readRocDacs: M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C0.dat .. M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C15.dat
[11:32:53.879] INFO: readTbmDacs: M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/tbmParameters_C0a.dat .. M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/tbmParameters_C0b.dat
[11:32:53.879] INFO: readMaskFile: M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/defaultMaskFile.dat
[11:32:53.879] INFO: readTrimFile: M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters_C0.dat .. M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters_C15.dat
[11:32:53.952] INFO: clk: 4
[11:32:53.952] INFO: ctr: 4
[11:32:53.952] INFO: sda: 19
[11:32:53.952] INFO: tin: 9
[11:32:53.952] INFO: level: 15
[11:32:53.952] INFO: triggerdelay: 0
[11:32:53.952] QUIET: Instanciating API for pxar prod-10+20~g6580e80
[11:32:53.952] INFO: Log level: INFO
[11:32:53.963] INFO: Found DTB DTB_WS8ZAW
[11:32:53.976] QUIET: Connection to board DTB_WS8ZAW opened.
[11:32:53.979] INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 85
HW version: DTB1.2
FW version: 4.2
SW version: 4.4
USB id: DTB_WS8ZAW
MAC address: 40D855118055
Hostname: pixelDTB085
Comment:
------------------------------------------------------
[11:32:53.982] INFO: RPC call hashes of host and DTB match: 397073690
[11:32:55.579] INFO: DUT info:
[11:32:55.579] INFO: The DUT currently contains the following objects:
[11:32:55.579] INFO: 2 TBM Cores tbm08c (2 ON)
[11:32:55.579] INFO: TBM Core alpha (0): 7 registers set
[11:32:55.579] INFO: TBM Core beta (1): 7 registers set
[11:32:55.579] INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[11:32:55.579] INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.579] INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.579] INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.579] INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.579] INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.579] INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.579] INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.579] INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.579] INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.579] INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.579] INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.579] INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.579] INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.580] INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.580] INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.580] INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[11:32:55.981] INFO: enter 'restricted' command line mode
[11:32:55.981] INFO: enter test to run
[11:32:55.981] INFO: test: Pretest no parameter change
[11:32:55.981] INFO: running: pretest
[11:32:55.987] INFO: ######################################################################
[11:32:55.987] INFO: PixTestPretest::doTest()
[11:32:55.987] INFO: ######################################################################
[11:32:55.989] INFO: ----------------------------------------------------------------------
[11:32:55.989] INFO: PixTestPretest::programROC()
[11:32:55.989] INFO: ----------------------------------------------------------------------
[11:33:14.007] INFO: PixTestPretest::programROC() done: ROCs are all programmable
[11:33:14.007] INFO: IA differences per ROC: 17.7 18.5 21.7 19.3 19.3 17.7 20.9 19.3 17.7 18.5 19.3 17.7 22.5 20.9 20.9 20.1
[11:33:14.061] INFO: ----------------------------------------------------------------------
[11:33:14.061] INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[11:33:14.061] INFO: ----------------------------------------------------------------------
[11:33:17.736] INFO: PixTestPretest::setVana() done, Module Ia 384.3 mA = 24.0187 mA/ROC
[11:33:17.738] INFO: ----------------------------------------------------------------------
[11:33:17.738] INFO: PixTestPretest::findTiming()
[11:33:17.738] INFO: ----------------------------------------------------------------------
[11:33:17.738] INFO: PixTestCmd::init()
[11:33:18.365] WARNING: Not unmasking DUT, not setting Calibrate bits!
[11:34:54.507] INFO: TBM phases: 160MHz: 7, 400MHz: 5, TBM delays: ROC(0/1):4, header/trailer: 1, token: 1
[11:34:54.507] INFO: (success/tries = 100/100), width = 5
[11:34:54.509] INFO: ----------------------------------------------------------------------
[11:34:54.509] INFO: PixTestPretest::findWorkingPixel()
[11:34:54.509] INFO: ----------------------------------------------------------------------
[11:34:54.649] INFO: Expecting 231680 events.
[11:34:59.837] ERROR: <datapipe.cc/CheckEventValidity:L480> Channel 0 Number of ROCs (1) != Token Chain Length (8)
[11:34:59.840] ERROR: <datapipe.cc/CheckEventID:L453> Channel 0 Event ID mismatch: local ID (21) != TBM ID (2)
[11:35:02.573] INFO: 231680 events read in total (7145ms).
[11:35:02.578] INFO: Test took 8066ms.
[11:35:03.043] INFO: Found working pixel in all ROCs: col/row = 12/22
[11:35:03.084] INFO: ----------------------------------------------------------------------
[11:35:03.084] INFO: PixTestPretest::setVthrCompCalDel()
[11:35:03.084] INFO: ----------------------------------------------------------------------
[11:35:03.221] INFO: Expecting 231680 events.
[11:35:11.081] INFO: 231680 events read in total (7081ms).
[11:35:11.085] INFO: Test took 7996ms.
[11:35:11.572] INFO: PixTestPretest::setVthrCompCalDel() done
[11:35:11.572] INFO: CalDel: 113 110 143 136 144 125 136 114 139 126 118 137 144 151 150 126
[11:35:11.572] INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[11:35:11.575] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C0.dat
[11:35:11.575] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C1.dat
[11:35:11.575] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C2.dat
[11:35:11.576] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C3.dat
[11:35:11.576] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C4.dat
[11:35:11.576] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C5.dat
[11:35:11.576] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C6.dat
[11:35:11.576] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C7.dat
[11:35:11.577] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C8.dat
[11:35:11.577] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C9.dat
[11:35:11.577] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C10.dat
[11:35:11.577] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C11.dat
[11:35:11.577] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C12.dat
[11:35:11.577] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C13.dat
[11:35:11.578] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C14.dat
[11:35:11.578] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters_C15.dat
[11:35:11.578] INFO: write tbm parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/tbmParameters_C0a.dat
[11:35:11.578] INFO: write tbm parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/tbmParameters_C0b.dat
[11:35:11.578] INFO: PixTestPretest::doTest() done, duration: 135 seconds
[11:35:11.641] INFO: enter test to run
[11:35:11.641] INFO: test: FullTest no parameter change
[11:35:11.641] INFO: running: fulltest
[11:35:11.641] INFO: ######################################################################
[11:35:11.641] INFO: PixTestFullTest::doTest()
[11:35:11.641] INFO: ######################################################################
[11:35:11.643] INFO: ######################################################################
[11:35:11.643] INFO: PixTestAlive::doTest()
[11:35:11.643] INFO: ######################################################################
[11:35:11.644] INFO: ----------------------------------------------------------------------
[11:35:11.644] INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:35:11.644] INFO: ----------------------------------------------------------------------
[11:35:12.002] INFO: Expecting 41600 events.
[11:35:16.141] INFO: 41600 events read in total (3360ms).
[11:35:16.142] INFO: Test took 4496ms.
[11:35:16.148] INFO: Fetched DAQ statistics. Counters are being reset now.
[11:35:16.593] INFO: PixTestAlive::aliveTest() done
[11:35:16.593] INFO: number of dead pixels per ROC: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:35:16.595] INFO: ----------------------------------------------------------------------
[11:35:16.595] INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:35:16.595] INFO: ----------------------------------------------------------------------
[11:35:16.957] INFO: Expecting 41600 events.
[11:35:19.894] INFO: 41600 events read in total (2158ms).
[11:35:19.895] INFO: Test took 3299ms.
[11:35:19.895] INFO: Fetched DAQ statistics. Counters are being reset now.
[11:35:19.895] INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[11:35:20.369] INFO: PixTestAlive::maskTest() done
[11:35:20.369] INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:35:20.371] INFO: ----------------------------------------------------------------------
[11:35:20.371] INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[11:35:20.371] INFO: ----------------------------------------------------------------------
[11:35:20.728] INFO: Expecting 41600 events.
[11:35:24.814] INFO: 41600 events read in total (3307ms).
[11:35:24.815] INFO: Test took 4442ms.
[11:35:24.821] INFO: Fetched DAQ statistics. Counters are being reset now.
[11:35:25.268] INFO: PixTestAlive::addressDecodingTest() done
[11:35:25.268] INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[11:35:25.268] INFO: PixTestAlive::doTest() done, duration: 13 seconds
[11:35:25.277] INFO: ######################################################################
[11:35:25.277] INFO: PixTestBBMap::doTest() Ntrig = 16, VcalS = 250 (high range)
[11:35:25.277] INFO: ######################################################################
[11:35:25.280] INFO: ---> dac: VthrComp name: calSMap ntrig: 16 dacrange: 0 .. 149 (-1/-1) hits flags = 2 (plus default)
[11:35:25.319] INFO: dacScan split into 1 runs with ntrig = 16
[11:35:25.319] INFO: run 1 of 1
[11:35:25.667] INFO: Expecting 9984000 events.
[11:35:53.730] INFO: 1208624 events read in total (27285ms).
[11:36:20.810] INFO: 2401376 events read in total (54365ms).
[11:36:47.735] INFO: 3577824 events read in total (81290ms).
[11:37:14.292] INFO: 4741200 events read in total (107847ms).
[11:37:40.842] INFO: 5906976 events read in total (134397ms).
[11:38:07.398] INFO: 7079360 events read in total (160953ms).
[11:38:33.414] INFO: 8258528 events read in total (186969ms).
[11:39:00.082] INFO: 9445488 events read in total (213637ms).
[11:39:12.356] INFO: 9984000 events read in total (225912ms).
[11:39:12.399] INFO: Test took 227080ms.
[11:39:12.497] INFO: Fetched DAQ statistics. Counters are being reset now.
[11:39:33.129] INFO: PixTestBBMap::doTest() done, duration: 247 seconds
[11:39:33.129] INFO: number of dead bumps (per ROC): 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0
[11:39:33.129] INFO: separation cut (per ROC): 125 117 119 115 113 117 112 119 110 108 113 103 114 106 104 98
[11:39:33.198] INFO: ######################################################################
[11:39:33.198] INFO: PixTestScurves::fullTest() ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:39:33.198] INFO: ######################################################################
[11:39:33.199] INFO: ----------------------------------------------------------------------
[11:39:33.199] INFO: PixTestScurves::scurves(Vcal), ntrig = 50, dacs/step = -1, ntrig/step = -1
[11:39:33.199] INFO: ----------------------------------------------------------------------
[11:39:33.199] INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 0 .. 149 (-1/-1) hits flags = 16 (plus default)
[11:39:33.209] INFO: dacScan split into 1 runs with ntrig = 50
[11:39:33.209] INFO: run 1 of 1
[11:39:33.556] INFO: Expecting 31200000 events.
[11:39:55.472] INFO: 1163900 events read in total (21136ms).
[11:40:18.850] INFO: 2309600 events read in total (44514ms).
[11:40:42.198] INFO: 3454850 events read in total (67862ms).
[11:41:05.542] INFO: 4596750 events read in total (91206ms).
[11:41:28.832] INFO: 5738300 events read in total (114496ms).
[11:41:52.051] INFO: 6879850 events read in total (137715ms).
[11:42:15.246] INFO: 8019850 events read in total (160910ms).
[11:42:38.387] INFO: 9156400 events read in total (184051ms).
[11:43:01.573] INFO: 10293700 events read in total (207237ms).
[11:43:24.705] INFO: 11430000 events read in total (230369ms).
[11:43:47.757] INFO: 12562200 events read in total (253421ms).
[11:44:10.781] INFO: 13694650 events read in total (276445ms).
[11:44:33.804] INFO: 14829050 events read in total (299468ms).
[11:44:56.739] INFO: 15956550 events read in total (322403ms).
[11:45:19.668] INFO: 17075350 events read in total (345332ms).
[11:45:42.480] INFO: 18192900 events read in total (368144ms).
[11:46:05.260] INFO: 19309450 events read in total (390924ms).
[11:46:28.144] INFO: 20421650 events read in total (413808ms).
[11:46:51.108] INFO: 21532700 events read in total (436772ms).
[11:47:14.015] INFO: 22642800 events read in total (459679ms).
[11:47:36.915] INFO: 23753600 events read in total (482579ms).
[11:47:59.900] INFO: 24865400 events read in total (505564ms).
[11:48:22.881] INFO: 25977750 events read in total (528545ms).
[11:48:45.876] INFO: 27088150 events read in total (551540ms).
[11:49:08.820] INFO: 28199550 events read in total (574484ms).
[11:49:31.771] INFO: 29310600 events read in total (597435ms).
[11:49:54.745] INFO: 30425950 events read in total (620409ms).
[11:50:10.502] INFO: 31200000 events read in total (636166ms).
[11:50:10.544] INFO: Test took 637335ms.
[11:50:10.643] INFO: Fetched DAQ statistics. Counters are being reset now.
[11:50:10.883] INFO: dumping ASCII scurve output file: SCurveData
[11:50:12.373] INFO: dumping ASCII scurve output file: SCurveData
[11:50:13.816] INFO: dumping ASCII scurve output file: SCurveData
[11:50:15.268] INFO: dumping ASCII scurve output file: SCurveData
[11:50:16.714] INFO: dumping ASCII scurve output file: SCurveData
[11:50:18.195] INFO: dumping ASCII scurve output file: SCurveData
[11:50:19.639] INFO: dumping ASCII scurve output file: SCurveData
[11:50:21.132] INFO: dumping ASCII scurve output file: SCurveData
[11:50:22.568] INFO: dumping ASCII scurve output file: SCurveData
[11:50:24.032] INFO: dumping ASCII scurve output file: SCurveData
[11:50:25.478] INFO: dumping ASCII scurve output file: SCurveData
[11:50:26.927] INFO: dumping ASCII scurve output file: SCurveData
[11:50:28.416] INFO: dumping ASCII scurve output file: SCurveData
[11:50:29.850] INFO: dumping ASCII scurve output file: SCurveData
[11:50:31.308] INFO: dumping ASCII scurve output file: SCurveData
[11:50:32.778] INFO: dumping ASCII scurve output file: SCurveData
[11:50:34.364] INFO: PixTestScurves::scurves() done
[11:50:34.364] INFO: Vcal mean: 90.82 92.96 85.96 90.62 80.17 89.32 73.76 97.92 83.21 89.29 89.52 79.69 95.71 84.50 83.49 72.94
[11:50:34.364] INFO: Vcal RMS: 5.40 5.65 5.07 5.51 4.28 5.32 4.61 5.55 5.03 5.82 5.53 4.40 5.34 4.97 5.37 4.96
[11:50:34.364] INFO: PixTestScurves::fullTest() done, duration: 661 seconds
[11:50:34.440] INFO: ######################################################################
[11:50:34.440] INFO: PixTestTrim::doTest()
[11:50:34.440] INFO: ######################################################################
[11:50:34.441] INFO: ----------------------------------------------------------------------
[11:50:34.441] INFO: PixTestTrim::trimTest() ntrig = 20, vcal = 35
[11:50:34.441] INFO: ----------------------------------------------------------------------
[11:50:34.517] INFO: ---> VthrComp thr map (minimal VthrComp)
[11:50:34.517] INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[11:50:34.528] INFO: dacScan split into 1 runs with ntrig = 20
[11:50:34.528] INFO: run 1 of 1
[11:50:34.889] INFO: Expecting 13312000 events.
[11:51:03.949] INFO: 1430520 events read in total (28276ms).
[11:51:32.103] INFO: 2853980 events read in total (56430ms).
[11:52:00.270] INFO: 4274040 events read in total (84597ms).
[11:52:28.330] INFO: 5684720 events read in total (112657ms).
[11:52:56.436] INFO: 7095820 events read in total (140763ms).
[11:53:24.562] INFO: 8514980 events read in total (168889ms).
[11:53:52.757] INFO: 9941220 events read in total (197084ms).
[11:54:20.996] INFO: 11367060 events read in total (225323ms).
[11:54:49.263] INFO: 12795140 events read in total (253590ms).
[11:54:59.752] INFO: 13312000 events read in total (264079ms).
[11:54:59.788] INFO: Test took 265260ms.
[11:54:59.848] INFO: Fetched DAQ statistics. Counters are being reset now.
[11:55:18.711] INFO: ROC 0 VthrComp = 96
[11:55:18.711] INFO: ROC 1 VthrComp = 97
[11:55:18.711] INFO: ROC 2 VthrComp = 91
[11:55:18.711] INFO: ROC 3 VthrComp = 91
[11:55:18.711] INFO: ROC 4 VthrComp = 86
[11:55:18.711] INFO: ROC 5 VthrComp = 96
[11:55:18.711] INFO: ROC 6 VthrComp = 81
[11:55:18.712] INFO: ROC 7 VthrComp = 101
[11:55:18.712] INFO: ROC 8 VthrComp = 87
[11:55:18.712] INFO: ROC 9 VthrComp = 91
[11:55:18.712] INFO: ROC 10 VthrComp = 91
[11:55:18.712] INFO: ROC 11 VthrComp = 84
[11:55:18.712] INFO: ROC 12 VthrComp = 98
[11:55:18.712] INFO: ROC 13 VthrComp = 89
[11:55:18.712] INFO: ROC 14 VthrComp = 87
[11:55:18.712] INFO: ROC 15 VthrComp = 76
[11:55:18.712] INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[11:55:18.713] INFO: ---> dac: vcal name: TrimThr1 ntrig: 20 dacrange: 0 .. 159 (-1/-1) hits flags = 16 (plus default)
[11:55:18.722] INFO: dacScan split into 1 runs with ntrig = 20
[11:55:18.722] INFO: run 1 of 1
[11:55:19.071] INFO: Expecting 13312000 events.
[11:55:42.370] INFO: 915100 events read in total (22520ms).
[11:56:05.803] INFO: 1827640 events read in total (45953ms).
[11:56:29.321] INFO: 2738240 events read in total (69471ms).
[11:56:52.794] INFO: 3650560 events read in total (92944ms).
[11:57:16.336] INFO: 4562100 events read in total (116486ms).
[11:57:39.894] INFO: 5475640 events read in total (140044ms).
[11:58:03.442] INFO: 6389300 events read in total (163592ms).
[11:58:26.935] INFO: 7297460 events read in total (187085ms).
[11:58:50.473] INFO: 8202560 events read in total (210623ms).
[11:59:13.975] INFO: 9105320 events read in total (234125ms).
[11:59:37.449] INFO: 10007580 events read in total (257599ms).
[12:00:00.959] INFO: 10908660 events read in total (281109ms).
[12:00:24.559] INFO: 11810880 events read in total (304709ms).
[12:00:48.174] INFO: 12712960 events read in total (328324ms).
[12:01:03.895] INFO: 13312000 events read in total (344045ms).
[12:01:03.957] INFO: Test took 345235ms.
[12:01:04.141] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:01:27.999] INFO: roc 0 with ID = 0 has maximal Vcal 58.291 for pixel 10/6 mean/min/max = 44.7782/31.2397/58.3167
[12:01:27.000] INFO: roc 1 with ID = 1 has maximal Vcal 58.517 for pixel 20/75 mean/min/max = 45.2181/31.7184/58.7178
[12:01:27.000] INFO: roc 2 with ID = 2 has maximal Vcal 58.689 for pixel 0/77 mean/min/max = 45.568/32.4279/58.7081
[12:01:27.000] INFO: roc 3 with ID = 3 has maximal Vcal 58.8345 for pixel 11/18 mean/min/max = 46.0158/32.8611/59.1705
[12:01:27.001] INFO: roc 4 with ID = 4 has maximal Vcal 56.8415 for pixel 9/55 mean/min/max = 44.4062/31.8844/56.9281
[12:01:27.001] INFO: roc 5 with ID = 5 has maximal Vcal 57.5547 for pixel 1/7 mean/min/max = 44.7591/31.8694/57.6488
[12:01:27.001] INFO: roc 6 with ID = 6 has maximal Vcal 56.7545 for pixel 0/1 mean/min/max = 44.3248/31.8428/56.8068
[12:01:27.001] INFO: roc 7 with ID = 7 has maximal Vcal 57.9474 for pixel 4/70 mean/min/max = 44.8929/31.7626/58.0233
[12:01:27.002] INFO: roc 8 with ID = 8 has maximal Vcal 57.8536 for pixel 20/11 mean/min/max = 45.0586/31.9778/58.1394
[12:01:28.002] INFO: roc 9 with ID = 9 has maximal Vcal 60.4256 for pixel 27/74 mean/min/max = 46.0439/31.6607/60.4272
[12:01:28.002] INFO: roc 10 with ID = 10 has maximal Vcal 60.0732 for pixel 45/1 mean/min/max = 46.4869/32.868/60.1058
[12:01:28.003] INFO: roc 11 with ID = 11 has maximal Vcal 57.0227 for pixel 6/68 mean/min/max = 44.6034/32.1638/57.0429
[12:01:28.003] INFO: roc 12 with ID = 12 has maximal Vcal 59.4097 for pixel 19/0 mean/min/max = 45.7685/32.0711/59.4659
[12:01:28.003] INFO: roc 13 with ID = 13 has maximal Vcal 57.3867 for pixel 23/1 mean/min/max = 44.9293/32.3543/57.5044
[12:01:28.004] INFO: roc 14 with ID = 14 has maximal Vcal 58.7928 for pixel 11/17 mean/min/max = 45.1815/31.4079/58.9552
[12:01:28.004] INFO: roc 15 with ID = 15 has maximal Vcal 59.789 for pixel 24/60 mean/min/max = 47.3094/34.8122/59.8067
[12:01:28.004] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:01:28.135] INFO: Expecting 1029120 events.
[12:01:45.478] INFO: 1029120 events read in total (16564ms).
[12:01:45.485] INFO: Expecting 1029120 events.
[12:02:03.994] INFO: 1029120 events read in total (17898ms).
[12:02:03.002] INFO: Expecting 1029120 events.
[12:02:22.557] INFO: 1029120 events read in total (17933ms).
[12:02:22.568] INFO: Expecting 1029120 events.
[12:02:40.996] INFO: 1029120 events read in total (17812ms).
[12:02:41.012] INFO: Expecting 1029120 events.
[12:02:59.432] INFO: 1029120 events read in total (17805ms).
[12:02:59.446] INFO: Expecting 1029120 events.
[12:03:17.979] INFO: 1029120 events read in total (17908ms).
[12:03:17.000] INFO: Expecting 1029120 events.
[12:03:36.457] INFO: 1029120 events read in total (17846ms).
[12:03:36.478] INFO: Expecting 1029120 events.
[12:03:54.921] INFO: 1029120 events read in total (17833ms).
[12:03:54.942] INFO: Expecting 1029120 events.
[12:04:13.492] INFO: 1029120 events read in total (17937ms).
[12:04:13.515] INFO: Expecting 1029120 events.
[12:04:32.077] INFO: 1029120 events read in total (17953ms).
[12:04:32.102] INFO: Expecting 1029120 events.
[12:04:50.657] INFO: 1029120 events read in total (17949ms).
[12:04:50.691] INFO: Expecting 1029120 events.
[12:05:09.286] INFO: 1029120 events read in total (17996ms).
[12:05:09.318] INFO: Expecting 1029120 events.
[12:05:27.858] INFO: 1029120 events read in total (17947ms).
[12:05:27.893] INFO: Expecting 1029120 events.
[12:05:46.503] INFO: 1029120 events read in total (18020ms).
[12:05:46.539] INFO: Expecting 1029120 events.
[12:06:05.083] INFO: 1029120 events read in total (17955ms).
[12:06:05.123] INFO: Expecting 1029120 events.
[12:06:23.597] INFO: 1029120 events read in total (17889ms).
[12:06:23.647] INFO: Test took 295643ms.
[12:06:24.703] INFO: ---> dac: vcal name: TrimThr2 ntrig: 20 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[12:06:24.713] INFO: dacScan split into 1 runs with ntrig = 20
[12:06:24.713] INFO: run 1 of 1
[12:06:25.069] INFO: Expecting 16640000 events.
[12:06:48.743] INFO: 840880 events read in total (22895ms).
[12:07:11.720] INFO: 1679940 events read in total (45872ms).
[12:07:34.683] INFO: 2517520 events read in total (68835ms).
[12:07:57.583] INFO: 3355720 events read in total (91735ms).
[12:08:20.016] INFO: 4194680 events read in total (114168ms).
[12:08:42.923] INFO: 5032660 events read in total (137075ms).
[12:09:05.782] INFO: 5871960 events read in total (159934ms).
[12:09:28.660] INFO: 6710900 events read in total (182812ms).
[12:09:51.540] INFO: 7550860 events read in total (205692ms).
[12:10:14.367] INFO: 8389940 events read in total (228519ms).
[12:10:37.122] INFO: 9222940 events read in total (251274ms).
[12:10:59.933] INFO: 10057020 events read in total (274085ms).
[12:11:22.672] INFO: 10888940 events read in total (296824ms).
[12:11:45.375] INFO: 11719560 events read in total (319527ms).
[12:12:08.067] INFO: 12550400 events read in total (342219ms).
[12:12:30.740] INFO: 13380780 events read in total (364892ms).
[12:12:53.505] INFO: 14211040 events read in total (387657ms).
[12:13:16.146] INFO: 15041000 events read in total (410298ms).
[12:13:38.845] INFO: 15871260 events read in total (432997ms).
[12:13:59.743] INFO: 16640000 events read in total (453895ms).
[12:13:59.820] INFO: Test took 455107ms.
[12:14:00.058] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:14:26.507] INFO: ---> TrimStepCorr4 extremal thresholds: 0.050423 .. 50.660789
[12:14:26.574] INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 20 dacrange: 0 .. 60 (-1/-1) hits flags = 16 (plus default)
[12:14:26.584] INFO: dacScan split into 1 runs with ntrig = 20
[12:14:26.584] INFO: run 1 of 1
[12:14:26.931] INFO: Expecting 5075200 events.
[12:14:51.471] INFO: 1152240 events read in total (23759ms).
[12:15:17.390] INFO: 2306440 events read in total (49678ms).
[12:15:43.056] INFO: 3454560 events read in total (75344ms).
[12:16:08.720] INFO: 4594080 events read in total (101008ms).
[12:16:19.875] INFO: 5075200 events read in total (112163ms).
[12:16:19.900] INFO: Test took 113317ms.
[12:16:19.947] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:16:33.823] INFO: ---> TrimStepCorr2 extremal thresholds: 15.159336 .. 45.517691
[12:16:33.894] INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 20 dacrange: 5 .. 55 (-1/-1) hits flags = 16 (plus default)
[12:16:33.908] INFO: dacScan split into 1 runs with ntrig = 20
[12:16:33.908] INFO: run 1 of 1
[12:16:34.262] INFO: Expecting 4243200 events.
[12:17:01.189] INFO: 1163480 events read in total (26134ms).
[12:17:26.749] INFO: 2327240 events read in total (51695ms).
[12:17:52.753] INFO: 3487220 events read in total (77698ms).
[12:18:09.901] INFO: 4243200 events read in total (94846ms).
[12:18:09.922] INFO: Test took 96014ms.
[12:18:09.961] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:18:23.155] INFO: ---> TrimStepCorr1a extremal thresholds: 19.288498 .. 42.904772
[12:18:23.229] INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 20 dacrange: 9 .. 52 (-1/-1) hits flags = 16 (plus default)
[12:18:23.239] INFO: dacScan split into 1 runs with ntrig = 20
[12:18:23.239] INFO: run 1 of 1
[12:18:23.588] INFO: Expecting 3660800 events.
[12:18:50.503] INFO: 1170220 events read in total (26127ms).
[12:19:16.844] INFO: 2339820 events read in total (52468ms).
[12:19:41.801] INFO: 3506700 events read in total (77425ms).
[12:19:45.395] INFO: 3660800 events read in total (81019ms).
[12:19:45.407] INFO: Test took 82168ms.
[12:19:45.437] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:19:58.205] INFO: ---> TrimStepCorr1b extremal thresholds: 21.826431 .. 42.477315
[12:19:58.274] INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 20 dacrange: 11 .. 52 (-1/-1) hits flags = 16 (plus default)
[12:19:58.283] INFO: dacScan split into 1 runs with ntrig = 20
[12:19:58.283] INFO: run 1 of 1
[12:19:58.632] INFO: Expecting 3494400 events.
[12:20:25.446] INFO: 1153080 events read in total (26035ms).
[12:20:51.549] INFO: 2305580 events read in total (52139ms).
[12:21:17.632] INFO: 3457300 events read in total (78221ms).
[12:21:18.921] INFO: 3494400 events read in total (79510ms).
[12:21:18.937] INFO: Test took 80653ms.
[12:21:18.978] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:21:31.831] INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[12:21:31.831] INFO: ---> dac: vcal name: TrimThrFinal ntrig: 20 dacrange: 15 .. 55 (-1/-1) hits flags = 16 (plus default)
[12:21:31.843] INFO: dacScan split into 1 runs with ntrig = 20
[12:21:31.843] INFO: run 1 of 1
[12:21:32.193] INFO: Expecting 3411200 events.
[12:21:57.540] INFO: 1074180 events read in total (24569ms).
[12:22:22.869] INFO: 2148020 events read in total (49898ms).
[12:22:48.265] INFO: 3220940 events read in total (75294ms).
[12:22:53.106] INFO: 3411200 events read in total (80135ms).
[12:22:53.122] INFO: Test took 81279ms.
[12:22:53.162] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:23:06.250] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C0.dat
[12:23:06.250] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C1.dat
[12:23:06.250] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C2.dat
[12:23:06.250] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C3.dat
[12:23:06.250] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C4.dat
[12:23:06.251] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C5.dat
[12:23:06.251] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C6.dat
[12:23:06.251] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C7.dat
[12:23:06.251] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C8.dat
[12:23:06.251] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C9.dat
[12:23:06.251] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C10.dat
[12:23:06.251] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C11.dat
[12:23:06.252] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C12.dat
[12:23:06.252] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C13.dat
[12:23:06.252] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C14.dat
[12:23:06.252] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C15.dat
[12:23:06.252] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C0.dat
[12:23:06.263] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C1.dat
[12:23:06.270] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C2.dat
[12:23:06.276] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C3.dat
[12:23:06.282] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C4.dat
[12:23:06.287] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C5.dat
[12:23:06.293] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C6.dat
[12:23:06.299] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C7.dat
[12:23:06.305] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C8.dat
[12:23:06.311] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C9.dat
[12:23:06.316] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C10.dat
[12:23:06.322] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C11.dat
[12:23:06.328] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C12.dat
[12:23:06.334] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C13.dat
[12:23:06.340] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C14.dat
[12:23:06.346] INFO: write trim parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/trimParameters35_C15.dat
[12:23:06.351] INFO: PixTestTrim::trimTest() done
[12:23:06.351] INFO: vtrim: 96 87 93 97 77 89 84 94 85 101 97 94 99 91 93 89
[12:23:06.351] INFO: vthrcomp: 96 97 91 91 86 96 81 101 87 91 91 84 98 89 87 76
[12:23:06.351] INFO: vcal mean: 34.97 34.93 34.96 34.93 34.99 35.02 34.95 34.98 34.95 35.00 34.99 34.98 34.96 34.97 34.96 35.01
[12:23:06.351] INFO: vcal RMS: 0.71 0.77 0.68 0.73 0.68 0.74 0.67 0.80 0.70 0.78 0.75 0.72 0.73 0.69 0.75 0.68
[12:23:06.351] INFO: bits mean: 9.48 9.67 8.97 9.00 9.22 9.60 9.29 9.66 9.46 9.26 8.90 9.51 9.33 9.37 9.33 8.42
[12:23:06.351] INFO: bits RMS: 2.82 2.66 2.86 2.78 2.94 2.74 2.88 2.69 2.77 2.77 2.74 2.71 2.72 2.74 2.88 2.61
[12:23:06.359] INFO: ----------------------------------------------------------------------
[12:23:06.359] INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[12:23:06.359] INFO: ----------------------------------------------------------------------
[12:23:06.362] INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (-1/-1) hits flags = 16 (plus default)
[12:23:06.377] INFO: dacScan split into 1 runs with ntrig = 10
[12:23:06.377] INFO: run 1 of 1
[12:23:06.729] INFO: Expecting 8320000 events.
[12:23:36.277] INFO: 1131680 events read in total (28770ms).
[12:24:05.324] INFO: 2253510 events read in total (57817ms).
[12:24:32.312] INFO: 3370440 events read in total (84805ms).
[12:25:01.297] INFO: 4481310 events read in total (113790ms).
[12:25:28.663] INFO: 5581570 events read in total (141156ms).
[12:25:57.174] INFO: 6679300 events read in total (169667ms).
[12:26:24.101] INFO: 7777850 events read in total (196594ms).
[12:26:38.328] INFO: 8320000 events read in total (210821ms).
[12:26:38.376] INFO: Test took 211999ms.
[12:26:38.506] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:27:05.855] INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 163 (-1/-1) hits flags = 16 (plus default)
[12:27:05.867] INFO: dacScan split into 1 runs with ntrig = 10
[12:27:05.867] INFO: run 1 of 1
[12:27:06.215] INFO: Expecting 6822400 events.
[12:27:36.885] INFO: 1199850 events read in total (29891ms).
[12:28:04.694] INFO: 2386790 events read in total (57701ms).
[12:28:32.008] INFO: 3564580 events read in total (85014ms).
[12:28:59.959] INFO: 4725690 events read in total (112965ms).
[12:29:28.686] INFO: 5882410 events read in total (141692ms).
[12:29:51.976] INFO: 6822400 events read in total (164982ms).
[12:29:52.020] INFO: Test took 166153ms.
[12:29:52.112] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:30:16.153] INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 152 (-1/-1) hits flags = 16 (plus default)
[12:30:16.162] INFO: dacScan split into 1 runs with ntrig = 10
[12:30:16.162] INFO: run 1 of 1
[12:30:16.510] INFO: Expecting 6364800 events.
[12:30:47.653] INFO: 1250020 events read in total (30364ms).
[12:31:15.909] INFO: 2484910 events read in total (58620ms).
[12:31:45.338] INFO: 3704270 events read in total (88049ms).
[12:32:15.182] INFO: 4908040 events read in total (117893ms).
[12:32:45.070] INFO: 6111780 events read in total (147781ms).
[12:32:51.184] INFO: 6364800 events read in total (153895ms).
[12:32:51.219] INFO: Test took 155057ms.
[12:32:51.297] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:33:13.940] INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 150 (-1/-1) hits flags = 16 (plus default)
[12:33:13.954] INFO: dacScan split into 1 runs with ntrig = 10
[12:33:13.954] INFO: run 1 of 1
[12:33:14.307] INFO: Expecting 6281600 events.
[12:33:45.641] INFO: 1258790 events read in total (30555ms).
[12:34:15.955] INFO: 2501870 events read in total (60869ms).
[12:34:45.914] INFO: 3729140 events read in total (90828ms).
[12:35:14.541] INFO: 4940080 events read in total (119455ms).
[12:35:44.541] INFO: 6151750 events read in total (149455ms).
[12:35:48.093] INFO: 6281600 events read in total (153007ms).
[12:35:48.124] INFO: Test took 154169ms.
[12:35:48.199] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:36:10.590] INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 151 (-1/-1) hits flags = 16 (plus default)
[12:36:10.599] INFO: dacScan split into 1 runs with ntrig = 10
[12:36:10.599] INFO: run 1 of 1
[12:36:10.948] INFO: Expecting 6323200 events.
[12:36:40.089] INFO: 1252230 events read in total (28363ms).
[12:37:10.495] INFO: 2489160 events read in total (58769ms).
[12:37:40.664] INFO: 3710060 events read in total (88939ms).
[12:38:10.686] INFO: 4915470 events read in total (118960ms).
[12:38:38.601] INFO: 6121400 events read in total (146875ms).
[12:38:43.689] INFO: 6323200 events read in total (151963ms).
[12:38:43.721] INFO: Test took 153122ms.
[12:38:43.797] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:06.436] INFO: PixTestTrim::trimBitTest() done
[12:39:06.438] INFO: PixTestTrim::doTest() done, duration: 2911 seconds
[12:39:07.098] INFO: ######################################################################
[12:39:07.098] INFO: PixTestPhOptimization::doTest() Ntrig = 16
[12:39:07.098] INFO: ######################################################################
[12:39:07.448] INFO: Expecting 41600 events.
[12:39:11.590] INFO: 41600 events read in total (3363ms).
[12:39:11.590] INFO: Test took 4491ms.
[12:39:11.599] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:12.364] INFO: Expecting 41600 events.
[12:39:16.543] INFO: 41600 events read in total (3401ms).
[12:39:16.544] INFO: Test took 4536ms.
[12:39:16.550] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:17.047] INFO: Expecting 41600 events.
[12:39:21.226] INFO: 41600 events read in total (3401ms).
[12:39:21.227] INFO: Test took 4568ms.
[12:39:21.233] INFO: Fetched DAQ statistics. Counters are being reset now.
[12:39:21.240] INFO: The DUT currently contains the following objects:
[12:39:21.240] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:21.240] INFO: TBM Core alpha (0): 7 registers set
[12:39:21.240] INFO: TBM Core beta (1): 7 registers set
[12:39:21.240] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:21.240] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.240] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:21.728] INFO: Expecting 2560 events.
[12:39:22.755] INFO: 2560 events read in total (249ms).
[12:39:22.755] INFO: Test took 1515ms.
[12:39:22.755] INFO: The DUT currently contains the following objects:
[12:39:22.755] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:22.755] INFO: TBM Core alpha (0): 7 registers set
[12:39:22.755] INFO: TBM Core beta (1): 7 registers set
[12:39:22.755] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:22.755] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:22.756] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:23.327] INFO: Expecting 2560 events.
[12:39:24.353] INFO: 2560 events read in total (248ms).
[12:39:24.353] INFO: Test took 1597ms.
[12:39:24.353] INFO: The DUT currently contains the following objects:
[12:39:24.353] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:24.353] INFO: TBM Core alpha (0): 7 registers set
[12:39:24.353] INFO: TBM Core beta (1): 7 registers set
[12:39:24.353] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:24.353] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.353] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.354] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:24.925] INFO: Expecting 2560 events.
[12:39:25.951] INFO: 2560 events read in total (248ms).
[12:39:25.951] INFO: Test took 1597ms.
[12:39:25.951] INFO: The DUT currently contains the following objects:
[12:39:25.951] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:25.951] INFO: TBM Core alpha (0): 7 registers set
[12:39:25.951] INFO: TBM Core beta (1): 7 registers set
[12:39:25.951] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:25.952] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:25.952] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:26.523] INFO: Expecting 2560 events.
[12:39:27.548] INFO: 2560 events read in total (247ms).
[12:39:27.548] INFO: Test took 1596ms.
[12:39:27.548] INFO: The DUT currently contains the following objects:
[12:39:27.548] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:27.548] INFO: TBM Core alpha (0): 7 registers set
[12:39:27.548] INFO: TBM Core beta (1): 7 registers set
[12:39:27.548] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:27.548] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:27.549] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:28.119] INFO: Expecting 2560 events.
[12:39:29.146] INFO: 2560 events read in total (248ms).
[12:39:29.146] INFO: Test took 1597ms.
[12:39:29.147] INFO: The DUT currently contains the following objects:
[12:39:29.147] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:29.147] INFO: TBM Core alpha (0): 7 registers set
[12:39:29.147] INFO: TBM Core beta (1): 7 registers set
[12:39:29.147] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:29.147] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.147] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:29.718] INFO: Expecting 2560 events.
[12:39:30.743] INFO: 2560 events read in total (246ms).
[12:39:30.743] INFO: Test took 1596ms.
[12:39:30.744] INFO: The DUT currently contains the following objects:
[12:39:30.744] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:30.744] INFO: TBM Core alpha (0): 7 registers set
[12:39:30.744] INFO: TBM Core beta (1): 7 registers set
[12:39:30.744] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:30.744] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:30.744] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:31.315] INFO: Expecting 2560 events.
[12:39:32.341] INFO: 2560 events read in total (247ms).
[12:39:32.342] INFO: Test took 1598ms.
[12:39:32.342] INFO: The DUT currently contains the following objects:
[12:39:32.342] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:32.342] INFO: TBM Core alpha (0): 7 registers set
[12:39:32.342] INFO: TBM Core beta (1): 7 registers set
[12:39:32.342] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:32.342] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.342] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.343] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:32.913] INFO: Expecting 2560 events.
[12:39:33.939] INFO: 2560 events read in total (247ms).
[12:39:33.939] INFO: Test took 1596ms.
[12:39:33.940] INFO: The DUT currently contains the following objects:
[12:39:33.940] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:33.940] INFO: TBM Core alpha (0): 7 registers set
[12:39:33.940] INFO: TBM Core beta (1): 7 registers set
[12:39:33.940] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:33.940] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:33.940] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:34.511] INFO: Expecting 2560 events.
[12:39:35.538] INFO: 2560 events read in total (248ms).
[12:39:35.538] INFO: Test took 1598ms.
[12:39:35.538] INFO: The DUT currently contains the following objects:
[12:39:35.538] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:35.538] INFO: TBM Core alpha (0): 7 registers set
[12:39:35.538] INFO: TBM Core beta (1): 7 registers set
[12:39:35.538] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:35.538] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.538] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:35.539] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:36.110] INFO: Expecting 2560 events.
[12:39:37.136] INFO: 2560 events read in total (248ms).
[12:39:37.137] INFO: Test took 1598ms.
[12:39:37.137] INFO: The DUT currently contains the following objects:
[12:39:37.137] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:37.137] INFO: TBM Core alpha (0): 7 registers set
[12:39:37.137] INFO: TBM Core beta (1): 7 registers set
[12:39:37.137] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:37.137] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.137] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.138] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:37.709] INFO: Expecting 2560 events.
[12:39:38.736] INFO: 2560 events read in total (249ms).
[12:39:38.736] INFO: Test took 1598ms.
[12:39:38.736] INFO: The DUT currently contains the following objects:
[12:39:38.737] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:38.737] INFO: TBM Core alpha (0): 7 registers set
[12:39:38.737] INFO: TBM Core beta (1): 7 registers set
[12:39:38.737] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:38.737] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:38.737] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:39.308] INFO: Expecting 2560 events.
[12:39:40.335] INFO: 2560 events read in total (249ms).
[12:39:40.335] INFO: Test took 1598ms.
[12:39:40.336] INFO: The DUT currently contains the following objects:
[12:39:40.336] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:40.336] INFO: TBM Core alpha (0): 7 registers set
[12:39:40.336] INFO: TBM Core beta (1): 7 registers set
[12:39:40.336] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:40.336] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.336] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:40.908] INFO: Expecting 2560 events.
[12:39:41.933] INFO: 2560 events read in total (248ms).
[12:39:41.934] INFO: Test took 1598ms.
[12:39:41.934] INFO: The DUT currently contains the following objects:
[12:39:41.934] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:41.934] INFO: TBM Core alpha (0): 7 registers set
[12:39:41.934] INFO: TBM Core beta (1): 7 registers set
[12:39:41.934] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:41.934] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.934] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.934] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.934] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.934] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.934] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.935] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.935] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.935] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.935] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.935] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.935] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.935] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.935] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.935] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:41.935] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:42.505] INFO: Expecting 2560 events.
[12:39:43.532] INFO: 2560 events read in total (248ms).
[12:39:43.532] INFO: Test took 1597ms.
[12:39:43.532] INFO: The DUT currently contains the following objects:
[12:39:43.532] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:43.532] INFO: TBM Core alpha (0): 7 registers set
[12:39:43.532] INFO: TBM Core beta (1): 7 registers set
[12:39:43.532] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:43.532] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.532] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.532] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.532] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.532] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.532] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.533] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.533] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.533] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.533] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.533] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.533] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.533] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.533] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.533] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:43.533] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:44.104] INFO: Expecting 2560 events.
[12:39:45.131] INFO: 2560 events read in total (249ms).
[12:39:45.131] INFO: Test took 1598ms.
[12:39:45.132] INFO: The DUT currently contains the following objects:
[12:39:45.132] INFO: 2 TBM Cores tbm08c (2 ON)
[12:39:45.132] INFO: TBM Core alpha (0): 7 registers set
[12:39:45.132] INFO: TBM Core beta (1): 7 registers set
[12:39:45.132] INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[12:39:45.132] INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.132] INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[12:39:45.703] INFO: Expecting 2560 events.
[12:39:46.729] INFO: 2560 events read in total (248ms).
[12:39:46.729] INFO: Test took 1597ms.
[12:39:46.733] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:39:47.303] INFO: Expecting 655360 events.
[12:40:00.259] INFO: 655360 events read in total (12177ms).
[12:40:00.269] INFO: Expecting 655360 events.
[12:40:12.504] INFO: 655360 events read in total (11655ms).
[12:40:12.519] INFO: Expecting 655360 events.
[12:40:24.300] INFO: 655360 events read in total (11198ms).
[12:40:24.319] INFO: Expecting 655360 events.
[12:40:36.197] INFO: 655360 events read in total (11299ms).
[12:40:36.222] INFO: Expecting 655360 events.
[12:40:48.967] INFO: 655360 events read in total (12179ms).
[12:40:49.004] INFO: Expecting 655360 events.
[12:41:01.793] INFO: 655360 events read in total (12232ms).
[12:41:01.826] INFO: Expecting 655360 events.
[12:41:14.548] INFO: 655360 events read in total (12163ms).
[12:41:14.583] INFO: Expecting 655360 events.
[12:41:27.355] INFO: 655360 events read in total (12214ms).
[12:41:27.394] INFO: Expecting 655360 events.
[12:41:39.321] INFO: 655360 events read in total (11371ms).
[12:41:39.364] INFO: Expecting 655360 events.
[12:41:51.168] INFO: 655360 events read in total (11253ms).
[12:41:51.218] INFO: Expecting 655360 events.
[12:42:03.048] INFO: 655360 events read in total (11283ms).
[12:42:03.100] INFO: Expecting 655360 events.
[12:42:14.924] INFO: 655360 events read in total (11279ms).
[12:42:14.980] INFO: Expecting 655360 events.
[12:42:27.736] INFO: 655360 events read in total (12213ms).
[12:42:27.801] INFO: Expecting 655360 events.
[12:42:40.593] INFO: 655360 events read in total (12266ms).
[12:42:40.661] INFO: Expecting 655360 events.
[12:42:53.382] INFO: 655360 events read in total (12195ms).
[12:42:53.451] INFO: Expecting 655360 events.
[12:43:06.208] INFO: 655360 events read in total (12230ms).
[12:43:06.284] INFO: Test took 199552ms.
[12:43:06.383] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:43:06.748] INFO: Expecting 655360 events.
[12:43:19.708] INFO: 655360 events read in total (12181ms).
[12:43:19.718] INFO: Expecting 655360 events.
[12:43:32.471] INFO: 655360 events read in total (12169ms).
[12:43:32.490] INFO: Expecting 655360 events.
[12:43:45.354] INFO: 655360 events read in total (12285ms).
[12:43:45.373] INFO: Expecting 655360 events.
[12:43:57.106] INFO: 655360 events read in total (11161ms).
[12:43:57.129] INFO: Expecting 655360 events.
[12:44:09.052] INFO: 655360 events read in total (11346ms).
[12:44:09.079] INFO: Expecting 655360 events.
[12:44:21.581] INFO: 655360 events read in total (11938ms).
[12:44:21.612] INFO: Expecting 655360 events.
[12:44:34.402] INFO: 655360 events read in total (12229ms).
[12:44:34.442] INFO: Expecting 655360 events.
[12:44:46.213] INFO: 655360 events read in total (11219ms).
[12:44:46.252] INFO: Expecting 655360 events.
[12:44:58.114] INFO: 655360 events read in total (11299ms).
[12:44:58.157] INFO: Expecting 655360 events.
[12:45:10.012] INFO: 655360 events read in total (11297ms).
[12:45:10.060] INFO: Expecting 655360 events.
[12:45:21.960] INFO: 655360 events read in total (11345ms).
[12:45:22.011] INFO: Expecting 655360 events.
[12:45:34.742] INFO: 655360 events read in total (12183ms).
[12:45:34.800] INFO: Expecting 655360 events.
[12:45:47.527] INFO: 655360 events read in total (12192ms).
[12:45:47.587] INFO: Expecting 655360 events.
[12:46:00.387] INFO: 655360 events read in total (12255ms).
[12:46:00.453] INFO: Expecting 655360 events.
[12:46:13.201] INFO: 655360 events read in total (12221ms).
[12:46:13.276] INFO: Expecting 655360 events.
[12:46:26.031] INFO: 655360 events read in total (12229ms).
[12:46:26.104] INFO: Test took 199721ms.
[12:46:26.298] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.304] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.310] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.317] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.323] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.331] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.339] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.347] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.354] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.362] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.370] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.377] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.384] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.391] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.398] INFO: safety margin for low PH: adding 1, margin is now 21
[12:46:26.405] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.412] INFO: safety margin for low PH: adding 0, margin is now 20
[12:46:26.470] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C0.dat
[12:46:26.470] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C1.dat
[12:46:26.470] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C2.dat
[12:46:26.470] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C3.dat
[12:46:26.470] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C4.dat
[12:46:26.470] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C5.dat
[12:46:26.470] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C6.dat
[12:46:26.470] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C7.dat
[12:46:26.470] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C8.dat
[12:46:26.470] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C9.dat
[12:46:26.471] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C10.dat
[12:46:26.471] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C11.dat
[12:46:26.471] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C12.dat
[12:46:26.471] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C13.dat
[12:46:26.471] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C14.dat
[12:46:26.471] INFO: write dac parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/dacParameters35_C15.dat
[12:46:26.826] INFO: Expecting 41600 events.
[12:46:30.997] INFO: 41600 events read in total (3393ms).
[12:46:30.997] INFO: Test took 4523ms.
[12:46:31.737] INFO: Expecting 41600 events.
[12:46:35.885] INFO: 41600 events read in total (3370ms).
[12:46:35.886] INFO: Test took 4503ms.
[12:46:36.631] INFO: Expecting 41600 events.
[12:46:40.814] INFO: 41600 events read in total (3404ms).
[12:46:40.815] INFO: Test took 4539ms.
[12:46:41.203] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:41.335] INFO: Expecting 2560 events.
[12:46:42.360] INFO: 2560 events read in total (247ms).
[12:46:42.360] INFO: Test took 1157ms.
[12:46:42.362] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:42.933] INFO: Expecting 2560 events.
[12:46:43.958] INFO: 2560 events read in total (247ms).
[12:46:43.959] INFO: Test took 1597ms.
[12:46:43.961] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:44.531] INFO: Expecting 2560 events.
[12:46:45.558] INFO: 2560 events read in total (248ms).
[12:46:45.558] INFO: Test took 1597ms.
[12:46:45.560] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:46.131] INFO: Expecting 2560 events.
[12:46:47.156] INFO: 2560 events read in total (247ms).
[12:46:47.157] INFO: Test took 1597ms.
[12:46:47.159] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:47.729] INFO: Expecting 2560 events.
[12:46:48.751] INFO: 2560 events read in total (243ms).
[12:46:48.752] INFO: Test took 1593ms.
[12:46:48.754] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:49.325] INFO: Expecting 2560 events.
[12:46:50.351] INFO: 2560 events read in total (247ms).
[12:46:50.351] INFO: Test took 1597ms.
[12:46:50.354] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:50.924] INFO: Expecting 2560 events.
[12:46:51.951] INFO: 2560 events read in total (249ms).
[12:46:51.952] INFO: Test took 1599ms.
[12:46:51.954] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:52.524] INFO: Expecting 2560 events.
[12:46:53.550] INFO: 2560 events read in total (247ms).
[12:46:53.551] INFO: Test took 1597ms.
[12:46:53.553] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:54.123] INFO: Expecting 2560 events.
[12:46:55.149] INFO: 2560 events read in total (247ms).
[12:46:55.150] INFO: Test took 1597ms.
[12:46:55.152] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:55.722] INFO: Expecting 2560 events.
[12:46:56.748] INFO: 2560 events read in total (247ms).
[12:46:56.748] INFO: Test took 1596ms.
[12:46:56.751] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:57.321] INFO: Expecting 2560 events.
[12:46:58.346] INFO: 2560 events read in total (246ms).
[12:46:58.346] INFO: Test took 1595ms.
[12:46:58.348] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:46:58.918] INFO: Expecting 2560 events.
[12:46:59.944] INFO: 2560 events read in total (247ms).
[12:46:59.944] INFO: Test took 1596ms.
[12:46:59.947] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:00.517] INFO: Expecting 2560 events.
[12:47:01.544] INFO: 2560 events read in total (248ms).
[12:47:01.544] INFO: Test took 1598ms.
[12:47:01.547] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:02.117] INFO: Expecting 2560 events.
[12:47:03.144] INFO: 2560 events read in total (248ms).
[12:47:03.144] INFO: Test took 1597ms.
[12:47:03.147] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:03.717] INFO: Expecting 2560 events.
[12:47:04.744] INFO: 2560 events read in total (248ms).
[12:47:04.744] INFO: Test took 1597ms.
[12:47:04.747] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:05.317] INFO: Expecting 2560 events.
[12:47:06.344] INFO: 2560 events read in total (249ms).
[12:47:06.345] INFO: Test took 1599ms.
[12:47:06.347] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:06.917] INFO: Expecting 2560 events.
[12:47:07.943] INFO: 2560 events read in total (247ms).
[12:47:07.944] INFO: Test took 1597ms.
[12:47:07.946] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:08.516] INFO: Expecting 2560 events.
[12:47:09.543] INFO: 2560 events read in total (248ms).
[12:47:09.543] INFO: Test took 1597ms.
[12:47:09.546] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:10.116] INFO: Expecting 2560 events.
[12:47:11.142] INFO: 2560 events read in total (248ms).
[12:47:11.143] INFO: Test took 1598ms.
[12:47:11.145] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:11.716] INFO: Expecting 2560 events.
[12:47:12.742] INFO: 2560 events read in total (248ms).
[12:47:12.743] INFO: Test took 1598ms.
[12:47:12.745] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:13.315] INFO: Expecting 2560 events.
[12:47:14.342] INFO: 2560 events read in total (248ms).
[12:47:14.343] INFO: Test took 1598ms.
[12:47:14.345] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:14.915] INFO: Expecting 2560 events.
[12:47:15.942] INFO: 2560 events read in total (248ms).
[12:47:15.943] INFO: Test took 1598ms.
[12:47:15.945] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:16.516] INFO: Expecting 2560 events.
[12:47:17.543] INFO: 2560 events read in total (248ms).
[12:47:17.543] INFO: Test took 1598ms.
[12:47:17.546] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:18.116] INFO: Expecting 2560 events.
[12:47:19.142] INFO: 2560 events read in total (248ms).
[12:47:19.142] INFO: Test took 1596ms.
[12:47:19.145] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:19.715] INFO: Expecting 2560 events.
[12:47:20.741] INFO: 2560 events read in total (248ms).
[12:47:20.742] INFO: Test took 1598ms.
[12:47:20.744] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:21.315] INFO: Expecting 2560 events.
[12:47:22.341] INFO: 2560 events read in total (248ms).
[12:47:22.341] INFO: Test took 1597ms.
[12:47:22.344] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:22.914] INFO: Expecting 2560 events.
[12:47:23.936] INFO: 2560 events read in total (244ms).
[12:47:23.936] INFO: Test took 1593ms.
[12:47:23.938] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:24.509] INFO: Expecting 2560 events.
[12:47:25.537] INFO: 2560 events read in total (249ms).
[12:47:25.537] INFO: Test took 1599ms.
[12:47:25.540] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:26.110] INFO: Expecting 2560 events.
[12:47:27.137] INFO: 2560 events read in total (249ms).
[12:47:27.137] INFO: Test took 1598ms.
[12:47:27.140] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:27.710] INFO: Expecting 2560 events.
[12:47:28.736] INFO: 2560 events read in total (248ms).
[12:47:28.737] INFO: Test took 1598ms.
[12:47:28.739] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:29.309] INFO: Expecting 2560 events.
[12:47:30.336] INFO: 2560 events read in total (248ms).
[12:47:30.336] INFO: Test took 1597ms.
[12:47:30.339] INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[12:47:30.909] INFO: Expecting 2560 events.
[12:47:31.932] INFO: 2560 events read in total (245ms).
[12:47:31.932] INFO: Test took 1594ms.
[12:47:32.710] INFO: PixTestPhOptimization::doTest() done, duration: 505 seconds
[12:47:32.710] INFO: PH scale (per ROC): 95 73 89 81 80 83 93 80 85 67 81 96 82 80 89 79
[12:47:32.710] INFO: PH offset (per ROC): 144 142 147 160 150 165 142 155 151 145 139 144 165 149 149 152
[12:47:32.884] INFO: ######################################################################
[12:47:32.884] INFO: PixTestGainPedestal::fullTest() ntrig = 1
[12:47:32.884] INFO: ######################################################################
[12:47:32.895] INFO: scanning low vcal = 10
[12:47:33.248] INFO: Expecting 4160 events.
[12:47:36.122] INFO: 4160 events read in total (2096ms).
[12:47:36.122] INFO: Test took 3227ms.
[12:47:36.124] INFO: scanning low vcal = 20
[12:47:36.695] INFO: Expecting 4160 events.
[12:47:39.568] INFO: 4160 events read in total (2094ms).
[12:47:39.569] INFO: Test took 3445ms.
[12:47:39.570] INFO: scanning low vcal = 30
[12:47:40.141] INFO: Expecting 4160 events.
[12:47:43.019] INFO: 4160 events read in total (2100ms).
[12:47:43.020] INFO: Test took 3450ms.
[12:47:43.022] INFO: scanning low vcal = 40
[12:47:43.591] INFO: Expecting 4160 events.
[12:47:46.531] INFO: 4160 events read in total (2161ms).
[12:47:46.532] INFO: Test took 3510ms.
[12:47:46.534] INFO: scanning low vcal = 50
[12:47:47.079] INFO: Expecting 4160 events.
[12:47:50.023] INFO: 4160 events read in total (2166ms).
[12:47:50.023] INFO: Test took 3489ms.
[12:47:50.026] INFO: scanning low vcal = 60
[12:47:50.573] INFO: Expecting 4160 events.
[12:47:53.515] INFO: 4160 events read in total (2163ms).
[12:47:53.516] INFO: Test took 3490ms.
[12:47:53.519] INFO: scanning low vcal = 70
[12:47:54.066] INFO: Expecting 4160 events.
[12:47:56.000] INFO: 4160 events read in total (2155ms).
[12:47:56.000] INFO: Test took 3481ms.
[12:47:57.003] INFO: scanning low vcal = 80
[12:47:57.552] INFO: Expecting 4160 events.
[12:48:00.484] INFO: 4160 events read in total (2153ms).
[12:48:00.485] INFO: Test took 3482ms.
[12:48:00.488] INFO: scanning low vcal = 90
[12:48:01.037] INFO: Expecting 4160 events.
[12:48:04.046] INFO: 4160 events read in total (2230ms).
[12:48:04.046] INFO: Test took 3558ms.
[12:48:04.049] INFO: scanning low vcal = 100
[12:48:04.599] INFO: Expecting 4160 events.
[12:48:07.527] INFO: 4160 events read in total (2150ms).
[12:48:07.528] INFO: Test took 3479ms.
[12:48:07.530] INFO: scanning low vcal = 110
[12:48:08.080] INFO: Expecting 4160 events.
[12:48:11.008] INFO: 4160 events read in total (2150ms).
[12:48:11.008] INFO: Test took 3478ms.
[12:48:11.011] INFO: scanning low vcal = 120
[12:48:11.560] INFO: Expecting 4160 events.
[12:48:14.487] INFO: 4160 events read in total (2148ms).
[12:48:14.488] INFO: Test took 3477ms.
[12:48:14.490] INFO: scanning low vcal = 130
[12:48:15.040] INFO: Expecting 4160 events.
[12:48:17.972] INFO: 4160 events read in total (2153ms).
[12:48:17.972] INFO: Test took 3482ms.
[12:48:17.975] INFO: scanning low vcal = 140
[12:48:18.525] INFO: Expecting 4160 events.
[12:48:21.451] INFO: 4160 events read in total (2148ms).
[12:48:21.452] INFO: Test took 3477ms.
[12:48:21.455] INFO: scanning low vcal = 150
[12:48:22.003] INFO: Expecting 4160 events.
[12:48:24.929] INFO: 4160 events read in total (2147ms).
[12:48:24.930] INFO: Test took 3475ms.
[12:48:24.932] INFO: scanning low vcal = 160
[12:48:25.483] INFO: Expecting 4160 events.
[12:48:28.414] INFO: 4160 events read in total (2153ms).
[12:48:28.414] INFO: Test took 3481ms.
[12:48:28.417] INFO: scanning low vcal = 170
[12:48:28.966] INFO: Expecting 4160 events.
[12:48:31.891] INFO: 4160 events read in total (2146ms).
[12:48:31.892] INFO: Test took 3475ms.
[12:48:31.896] INFO: scanning low vcal = 180
[12:48:32.444] INFO: Expecting 4160 events.
[12:48:35.391] INFO: 4160 events read in total (2168ms).
[12:48:35.391] INFO: Test took 3495ms.
[12:48:35.394] INFO: scanning low vcal = 190
[12:48:35.936] INFO: Expecting 4160 events.
[12:48:38.882] INFO: 4160 events read in total (2167ms).
[12:48:38.883] INFO: Test took 3489ms.
[12:48:38.885] INFO: scanning low vcal = 200
[12:48:39.428] INFO: Expecting 4160 events.
[12:48:42.372] INFO: 4160 events read in total (2165ms).
[12:48:42.373] INFO: Test took 3488ms.
[12:48:42.375] INFO: scanning low vcal = 210
[12:48:42.918] INFO: Expecting 4160 events.
[12:48:45.860] INFO: 4160 events read in total (2163ms).
[12:48:45.860] INFO: Test took 3485ms.
[12:48:45.863] INFO: scanning low vcal = 220
[12:48:46.409] INFO: Expecting 4160 events.
[12:48:49.359] INFO: 4160 events read in total (2171ms).
[12:48:49.359] INFO: Test took 3496ms.
[12:48:49.362] INFO: scanning low vcal = 230
[12:48:49.906] INFO: Expecting 4160 events.
[12:48:52.849] INFO: 4160 events read in total (2165ms).
[12:48:52.850] INFO: Test took 3488ms.
[12:48:52.852] INFO: scanning low vcal = 240
[12:48:53.396] INFO: Expecting 4160 events.
[12:48:56.341] INFO: 4160 events read in total (2167ms).
[12:48:56.342] INFO: Test took 3490ms.
[12:48:56.344] INFO: scanning low vcal = 250
[12:48:56.888] INFO: Expecting 4160 events.
[12:48:59.833] INFO: 4160 events read in total (2166ms).
[12:48:59.834] INFO: Test took 3490ms.
[12:48:59.838] INFO: scanning high vcal = 30 (= 210 in low range)
[12:49:00.379] INFO: Expecting 4160 events.
[12:49:03.326] INFO: 4160 events read in total (2168ms).
[12:49:03.327] INFO: Test took 3489ms.
[12:49:03.329] INFO: scanning high vcal = 50 (= 350 in low range)
[12:49:03.870] INFO: Expecting 4160 events.
[12:49:06.815] INFO: 4160 events read in total (2166ms).
[12:49:06.815] INFO: Test took 3486ms.
[12:49:06.818] INFO: scanning high vcal = 70 (= 490 in low range)
[12:49:07.361] INFO: Expecting 4160 events.
[12:49:10.313] INFO: 4160 events read in total (2173ms).
[12:49:10.313] INFO: Test took 3495ms.
[12:49:10.316] INFO: scanning high vcal = 90 (= 630 in low range)
[12:49:10.860] INFO: Expecting 4160 events.
[12:49:13.886] INFO: 4160 events read in total (2248ms).
[12:49:13.887] INFO: Test took 3571ms.
[12:49:13.889] INFO: scanning high vcal = 200 (= 1400 in low range)
[12:49:14.432] INFO: Expecting 4160 events.
[12:49:17.379] INFO: 4160 events read in total (2168ms).
[12:49:17.379] INFO: Test took 3490ms.
[12:49:17.874] INFO: PixTestGainPedestal::measure() done
[12:49:51.377] INFO: PixTestGainPedestal::fit() done
[12:49:51.377] INFO: non-linearity mean: 0.951 0.947 0.952 0.954 0.955 0.955 0.954 0.958 0.954 0.954 0.957 0.951 0.957 0.953 0.956 0.951
[12:49:51.377] INFO: non-linearity RMS: 0.006 0.006 0.007 0.006 0.006 0.006 0.006 0.006 0.005 0.006 0.006 0.007 0.006 0.005 0.006 0.007
[12:49:51.377] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C0.dat
[12:49:51.402] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C1.dat
[12:49:51.421] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C2.dat
[12:49:51.439] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C3.dat
[12:49:51.458] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C4.dat
[12:49:51.476] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C5.dat
[12:49:51.495] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C6.dat
[12:49:51.513] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C7.dat
[12:49:51.532] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C8.dat
[12:49:51.551] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C9.dat
[12:49:51.569] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C10.dat
[12:49:51.600] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C11.dat
[12:49:51.618] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C12.dat
[12:49:51.637] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C13.dat
[12:49:51.655] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C14.dat
[12:49:51.674] INFO: write gain/ped parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/phCalibrationFitErr35_C15.dat
[12:49:51.692] INFO: PixTestGainPedestal::doTest() done, duration: 138 seconds
[12:49:51.698] INFO: readReadbackCal: M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C0.dat .. M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C15.dat
[12:49:51.699] INFO: PixTestReadback::doTest() start.
[12:49:51.700] INFO: PixTestReadback::RES sent once
[12:50:04.255] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C0.dat
[12:50:04.255] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C1.dat
[12:50:04.255] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C2.dat
[12:50:04.255] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C3.dat
[12:50:04.255] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C4.dat
[12:50:04.255] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C5.dat
[12:50:04.255] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C6.dat
[12:50:04.255] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C7.dat
[12:50:04.255] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C8.dat
[12:50:04.255] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C9.dat
[12:50:04.256] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C10.dat
[12:50:04.256] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C11.dat
[12:50:04.256] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C12.dat
[12:50:04.256] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C13.dat
[12:50:04.256] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C14.dat
[12:50:04.256] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C15.dat
[12:50:04.291] INFO: PixTestPattern:: pg_setup set to default.
[12:50:04.292] INFO: PixTestReadback::RES sent once
[12:50:16.814] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C0.dat
[12:50:16.814] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C1.dat
[12:50:16.814] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C2.dat
[12:50:16.814] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C3.dat
[12:50:16.814] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C4.dat
[12:50:16.814] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C5.dat
[12:50:16.814] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C6.dat
[12:50:16.814] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C7.dat
[12:50:16.814] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C8.dat
[12:50:16.815] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C9.dat
[12:50:16.815] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C10.dat
[12:50:16.815] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C11.dat
[12:50:16.815] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C12.dat
[12:50:16.815] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C13.dat
[12:50:16.815] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C14.dat
[12:50:16.815] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C15.dat
[12:50:16.849] INFO: PixTestPattern:: pg_setup set to default.
[12:50:16.849] INFO: PixTestReadback::RES sent once
[12:50:26.507] INFO: PixTestPattern:: pg_setup set to default.
[12:50:26.507] INFO: Vbg will be calibrated using Vd calibration
[12:50:26.507] INFO: /*/*/*/*::: ROC 0: uncalibrated Vbg = 156.8calibrated Vbg = 1.22703 :::*/*/*/*/
[12:50:26.507] INFO: /*/*/*/*::: ROC 1: uncalibrated Vbg = 149.1calibrated Vbg = 1.21647 :::*/*/*/*/
[12:50:26.507] INFO: /*/*/*/*::: ROC 2: uncalibrated Vbg = 158calibrated Vbg = 1.22124 :::*/*/*/*/
[12:50:26.507] INFO: /*/*/*/*::: ROC 3: uncalibrated Vbg = 152.6calibrated Vbg = 1.2281 :::*/*/*/*/
[12:50:26.507] INFO: /*/*/*/*::: ROC 4: uncalibrated Vbg = 148.7calibrated Vbg = 1.23782 :::*/*/*/*/
[12:50:26.507] INFO: /*/*/*/*::: ROC 5: uncalibrated Vbg = 150.5calibrated Vbg = 1.24031 :::*/*/*/*/
[12:50:26.507] INFO: /*/*/*/*::: ROC 6: uncalibrated Vbg = 148.3calibrated Vbg = 1.23564 :::*/*/*/*/
[12:50:26.507] INFO: /*/*/*/*::: ROC 7: uncalibrated Vbg = 155.6calibrated Vbg = 1.23745 :::*/*/*/*/
[12:50:26.507] INFO: /*/*/*/*::: ROC 8: uncalibrated Vbg = 155.3calibrated Vbg = 1.24227 :::*/*/*/*/
[12:50:26.507] INFO: /*/*/*/*::: ROC 9: uncalibrated Vbg = 150.6calibrated Vbg = 1.23892 :::*/*/*/*/
[12:50:26.508] INFO: /*/*/*/*::: ROC 10: uncalibrated Vbg = 150.3calibrated Vbg = 1.23118 :::*/*/*/*/
[12:50:26.508] INFO: /*/*/*/*::: ROC 11: uncalibrated Vbg = 145.2calibrated Vbg = 1.23144 :::*/*/*/*/
[12:50:26.508] INFO: /*/*/*/*::: ROC 12: uncalibrated Vbg = 144.5calibrated Vbg = 1.22755 :::*/*/*/*/
[12:50:26.508] INFO: /*/*/*/*::: ROC 13: uncalibrated Vbg = 153calibrated Vbg = 1.22285 :::*/*/*/*/
[12:50:26.508] INFO: /*/*/*/*::: ROC 14: uncalibrated Vbg = 152.3calibrated Vbg = 1.22387 :::*/*/*/*/
[12:50:26.508] INFO: /*/*/*/*::: ROC 15: uncalibrated Vbg = 148.7calibrated Vbg = 1.22365 :::*/*/*/*/
[12:50:26.511] INFO: PixTestReadback::RES sent once
[12:53:36.245] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C0.dat
[12:53:36.245] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C1.dat
[12:53:36.245] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C2.dat
[12:53:36.245] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C3.dat
[12:53:36.245] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C4.dat
[12:53:36.245] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C5.dat
[12:53:36.245] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C6.dat
[12:53:36.245] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C7.dat
[12:53:36.246] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C8.dat
[12:53:36.246] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C9.dat
[12:53:36.246] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C10.dat
[12:53:36.246] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C11.dat
[12:53:36.246] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C12.dat
[12:53:36.246] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C13.dat
[12:53:36.246] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C14.dat
[12:53:36.246] INFO: write readback calibration parameters into M4077_FullQualification_2015-09-10_09h38m_1441870710/003_Fulltest_m20/readbackCal_C15.dat
[12:53:36.279] INFO: PixTestPattern:: pg_setup set to default.
[12:53:36.281] INFO: PixTestReadback::doTest() done
[12:53:36.297] INFO: enter test to run
[12:53:36.297] INFO: test: BB2 no parameter change
[12:53:36.297] INFO: running: bb2
[12:53:36.299] INFO: ######################################################################
[12:53:36.299] INFO: PixTestBB2Map::doTest() Ntrig = 16, VcalS = 255, PlWidth = 35
[12:53:36.299] INFO: ######################################################################
[12:53:36.301] INFO: ----------------------------------------------------------------------
[12:53:36.301] INFO: PixTestBB2Map::setVana() target Ia = 30 mA/ROC
[12:53:36.301] INFO: ----------------------------------------------------------------------
[12:53:55.873] INFO: PixTestBB2Map::setVana() done, Module Ia 473.5 mA = 29.5938 mA/ROC
[12:53:55.874] INFO: ----------------------------------------------------------------------
[12:53:55.874] INFO: PixTestBB2Map::setVthrCompCalDel()
[12:53:55.874] INFO: ----------------------------------------------------------------------
[12:53:56.017] INFO: Expecting 1048576 events.
[12:54:07.228] ERROR: <datapipe.cc/CheckEventValidity:L480> Channel 0 Number of ROCs (1) != Token Chain Length (8)
[12:54:07.230] ERROR: <datapipe.cc/CheckEventID:L453> Channel 0 Event ID mismatch: local ID (21) != TBM ID (2)
[12:54:16.523] INFO: 1048576 events read in total (19728ms).
[12:54:16.528] INFO: Test took 20647ms.
[12:54:16.961] INFO: PixTestBB2Map::setVthrCompCalDel() done
[12:54:16.961] INFO: CalDel: 117 116 143 138 144 124 134 113 135 125 119 131 147 149 150 123
[12:54:16.961] INFO: VthrComp: 114 114 110 116 112 116 103 120 105 105 104 101 123 105 108 92
[12:54:17.332] INFO: Expecting 8519680 events.
[12:54:45.137] INFO: 1336544 events read in total (27026ms).
[12:55:11.400] INFO: 2660544 events read in total (53289ms).
[12:55:39.735] INFO: 3966128 events read in total (81625ms).
[12:56:08.021] INFO: 5270800 events read in total (109910ms).
[12:56:36.441] INFO: 6582928 events read in total (138330ms).
[12:57:04.657] INFO: 7902976 events read in total (166546ms).
[12:57:17.975] INFO: 8519680 events read in total (179864ms).
[12:57:18.004] INFO: Test took 181020ms.
[12:57:18.640] INFO: Missing Bumps: 2 0 0 0 2 0 0 2 0 0 0 0 1 0 0 0
[12:57:18.640] INFO: Separation Cut: 42.60 43.13 41.93 43.89 43.41 38.41 42.90 40.69 37.20 35.05 38.36 36.95 45.00 34.64 33.80 33.31
[12:57:18.640] INFO: PixTestBB2Map::doTest() done,222 seconds
[12:57:18.947] INFO: enter test to run
[12:57:18.947] INFO: test: q no parameter change
[12:57:19.656] QUIET: Connection to board 85 closed.
[12:57:19.657] INFO: pXar: this is the end, my friend