[13:53:08.991] <TB2> INFO: *** Welcome to pxar ***
[13:53:08.991] <TB2> INFO: *** Today: 2015/07/28
[13:53:08.991] <TB2> INFO: readRocDacs: /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C0.dat .. /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C15.dat
[13:53:08.992] <TB2> INFO: readTbmDacs: /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//tbmParameters_C0a.dat .. /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//tbmParameters_C0b.dat
[13:53:08.992] <TB2> INFO: readMaskFile: /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//defaultMaskFile.dat
[13:53:08.992] <TB2> INFO: readTrimFile: /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters_C0.dat .. /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters_C15.dat
[13:53:09.056] <TB2> INFO: clk: 4
[13:53:09.056] <TB2> INFO: ctr: 4
[13:53:09.056] <TB2> INFO: sda: 19
[13:53:09.056] <TB2> INFO: tin: 9
[13:53:09.056] <TB2> INFO: level: 15
[13:53:09.056] <TB2> INFO: triggerdelay: 0
[13:53:09.056] <TB2> QUIET: Instanciating API for pxar v2.2.5+46~gdbe75a1
[13:53:09.056] <TB2> INFO: Log level: INFO
[13:53:09.064] <TB2> INFO: Found DTB DTB_WXC55Z
[13:53:09.076] <TB2> QUIET: Connection to board DTB_WXC55Z opened.
[13:53:09.079] <TB2> INFO: DTB startup information
--- DTB info------------------------------------------
Board id: 156
HW version: DTB1.2
FW version: 4.0
SW version: 4.0
USB id: DTB_WXC55Z
MAC address: 40D85511809C
Hostname: pixelDTB156
Comment:
------------------------------------------------------
[13:53:09.082] <TB2> INFO: RPC call hashes of host and DTB match: 447413373
[13:53:10.603] <TB2> INFO: DUT info:
[13:53:10.603] <TB2> INFO: The DUT currently contains the following objects:
[13:53:10.603] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[13:53:10.603] <TB2> INFO: TBM Core alpha (0): 7 registers set
[13:53:10.603] <TB2> INFO: TBM Core beta (1): 7 registers set
[13:53:10.603] <TB2> INFO: 16 ROCs psi46digv21respin (16 ON) with 4160 pixelConfigs
[13:53:10.603] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:10.603] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 0 masked, 0 active.
[13:53:11.005] <TB2> INFO: enter 'restricted' command line mode
[13:53:11.005] <TB2> INFO: enter test to run
[13:53:11.005] <TB2> INFO: test: pretest no parameter change
[13:53:11.005] <TB2> INFO: running: pretest
[13:53:11.014] <TB2> INFO: ######################################################################
[13:53:11.014] <TB2> INFO: PixTestPretest::doTest()
[13:53:11.014] <TB2> INFO: ######################################################################
[13:53:11.015] <TB2> INFO: ----------------------------------------------------------------------
[13:53:11.015] <TB2> INFO: PixTestPretest::programROC()
[13:53:11.015] <TB2> INFO: ----------------------------------------------------------------------
[13:53:29.032] <TB2> INFO: PixTestPretest::programROC() done: ROCs are all programmable
[13:53:29.032] <TB2> INFO: IA differences per ROC: 19.3 19.3 19.3 19.3 18.5 18.5 19.3 17.7 20.1 19.3 18.5 16.9 20.1 18.5 19.3 18.5
[13:53:29.095] <TB2> INFO: ----------------------------------------------------------------------
[13:53:29.095] <TB2> INFO: PixTestPretest::setVana() target Ia = 24 mA/ROC
[13:53:29.095] <TB2> INFO: ----------------------------------------------------------------------
[13:53:34.467] <TB2> INFO: PixTestPretest::setVana() done, Module Ia 385.1 mA = 24.0688 mA/ROC
[13:53:34.471] <TB2> INFO: ----------------------------------------------------------------------
[13:53:34.471] <TB2> INFO: PixTestPretest::findWorkingPixel()
[13:53:34.471] <TB2> INFO: ----------------------------------------------------------------------
[13:53:43.593] <TB2> INFO: Test took 9117ms.
[13:53:43.872] <TB2> INFO: Found working pixel in all ROCs: col/row = 12/22
[13:53:43.898] <TB2> INFO: ----------------------------------------------------------------------
[13:53:43.898] <TB2> INFO: PixTestPretest::setVthrCompCalDel()
[13:53:43.898] <TB2> INFO: ----------------------------------------------------------------------
[13:53:53.336] <TB2> INFO: Test took 9434ms.
[13:53:53.640] <TB2> INFO: PixTestPretest::setVthrCompCalDel() done
[13:53:53.640] <TB2> INFO: CalDel: 127 148 140 140 129 137 144 143 150 138 137 129 111 153 125 135
[13:53:53.640] <TB2> INFO: VthrComp: 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51 51
[13:53:53.644] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C0.dat
[13:53:53.645] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C1.dat
[13:53:53.645] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C2.dat
[13:53:53.645] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C3.dat
[13:53:53.645] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C4.dat
[13:53:53.646] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C5.dat
[13:53:53.646] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C6.dat
[13:53:53.646] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C7.dat
[13:53:53.647] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C8.dat
[13:53:53.647] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C9.dat
[13:53:53.647] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C10.dat
[13:53:53.647] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C11.dat
[13:53:53.648] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C12.dat
[13:53:53.648] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C13.dat
[13:53:53.648] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C14.dat
[13:53:53.648] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters_C15.dat
[13:53:53.649] <TB2> INFO: PixTestPretest::doTest() done, duration: 42 seconds
[13:53:53.766] <TB2> INFO: enter test to run
[13:53:53.766] <TB2> INFO: test: fulltest no parameter change
[13:53:53.766] <TB2> INFO: running: fulltest
[13:53:53.766] <TB2> INFO: ######################################################################
[13:53:53.766] <TB2> INFO: PixTestFullTest::doTest()
[13:53:53.766] <TB2> INFO: ######################################################################
[13:53:53.767] <TB2> INFO: ######################################################################
[13:53:53.767] <TB2> INFO: PixTestAlive::doTest()
[13:53:53.767] <TB2> INFO: ######################################################################
[13:53:53.769] <TB2> INFO: ----------------------------------------------------------------------
[13:53:53.769] <TB2> INFO: PixTestAlive::aliveTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:53:53.769] <TB2> INFO: ----------------------------------------------------------------------
[13:53:57.493] <TB2> INFO: Test took 3723ms.
[13:53:57.521] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:53:57.749] <TB2> INFO: PixTestAlive::aliveTest() done
[13:53:57.749] <TB2> INFO: number of dead pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
[13:53:57.751] <TB2> INFO: ----------------------------------------------------------------------
[13:53:57.751] <TB2> INFO: PixTestAlive::maskTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:53:57.751] <TB2> INFO: ----------------------------------------------------------------------
[13:54:00.683] <TB2> INFO: Test took 2931ms.
[13:54:00.686] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:54:00.687] <TB2> INFO: mask vs. old pixelAlive PixelAlive_C0_V0 .. PixelAlive_C15_V0
[13:54:00.906] <TB2> INFO: PixTestAlive::maskTest() done
[13:54:00.906] <TB2> INFO: number of mask-defect pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:54:00.907] <TB2> INFO: ----------------------------------------------------------------------
[13:54:00.907] <TB2> INFO: PixTestAlive::addressDecodingTest() ntrig = 10, vcal = 200 (ctrlreg = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
[13:54:00.907] <TB2> INFO: ----------------------------------------------------------------------
[13:54:04.616] <TB2> INFO: Test took 3707ms.
[13:54:04.641] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:54:04.868] <TB2> INFO: PixTestAlive::addressDecodingTest() done
[13:54:04.868] <TB2> INFO: number of address-decoding pixels (per ROC): 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[13:54:04.869] <TB2> INFO: PixTestAlive::doTest() done, duration: 11 seconds
[13:54:04.884] <TB2> INFO: ######################################################################
[13:54:04.884] <TB2> INFO: PixTestBBMap::doTest() Ntrig = 5, VcalS = 250 (high range)
[13:54:04.884] <TB2> INFO: ######################################################################
[13:54:04.887] <TB2> INFO: ---> dac: VthrComp name: calSMap ntrig: 5 dacrange: 0 .. 149 (30) hits flags = 2 (plus default)
[13:54:04.901] <TB2> INFO: dacScan step from 0 .. 29
[13:54:28.092] <TB2> INFO: Test took 23191ms.
[13:54:28.124] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:54:28.125] <TB2> INFO: dacScan step from 30 .. 59
[13:54:54.384] <TB2> INFO: Test took 26259ms.
[13:54:54.515] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:54:54.538] <TB2> INFO: dacScan step from 60 .. 89
[13:55:27.441] <TB2> INFO: Test took 32902ms.
[13:55:27.691] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:55:27.770] <TB2> INFO: dacScan step from 90 .. 119
[13:55:59.942] <TB2> INFO: Test took 32172ms.
[13:56:00.186] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:56:00.270] <TB2> INFO: dacScan step from 120 .. 149
[13:56:27.866] <TB2> INFO: Test took 27596ms.
[13:56:28.054] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:56:52.308] <TB2> INFO: PixTestBBMap::doTest() done, duration: 167 seconds
[13:56:52.308] <TB2> INFO: number of dead bumps (per ROC): 1 0 0 0 0 0 0 4 0 0 0 1 0 0 0 0
[13:56:52.308] <TB2> INFO: separation cut (per ROC): 93 87 85 90 86 70 82 87 77 89 84 85 86 83 96 83
[13:56:52.378] <TB2> INFO: ######################################################################
[13:56:52.378] <TB2> INFO: PixTestScurves::fullTest() ntrig = 50
[13:56:52.378] <TB2> INFO: ######################################################################
[13:56:52.378] <TB2> INFO: ----------------------------------------------------------------------
[13:56:52.378] <TB2> INFO: PixTestScurves::scurves(Vcal), ntrig = 50
[13:56:52.378] <TB2> INFO: ----------------------------------------------------------------------
[13:56:52.378] <TB2> INFO: ---> dac: Vcal name: scurveVcal ntrig: 50 dacrange: 0 .. 149 (4) hits flags = 16 (plus default)
[13:56:52.386] <TB2> INFO: dacScan step from 0 .. 3
[13:57:13.797] <TB2> INFO: Test took 21411ms.
[13:57:13.824] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:57:13.824] <TB2> INFO: dacScan step from 4 .. 7
[13:57:35.486] <TB2> INFO: Test took 21662ms.
[13:57:35.514] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:57:35.515] <TB2> INFO: dacScan step from 8 .. 11
[13:57:56.884] <TB2> INFO: Test took 21369ms.
[13:57:56.913] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:57:56.913] <TB2> INFO: dacScan step from 12 .. 15
[13:58:18.651] <TB2> INFO: Test took 21738ms.
[13:58:18.678] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:58:18.678] <TB2> INFO: dacScan step from 16 .. 19
[13:58:40.211] <TB2> INFO: Test took 21533ms.
[13:58:40.238] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:58:40.238] <TB2> INFO: dacScan step from 20 .. 23
[13:59:01.510] <TB2> INFO: Test took 21272ms.
[13:59:01.539] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:59:01.539] <TB2> INFO: dacScan step from 24 .. 27
[13:59:23.383] <TB2> INFO: Test took 21844ms.
[13:59:23.412] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:59:23.412] <TB2> INFO: dacScan step from 28 .. 31
[13:59:45.019] <TB2> INFO: Test took 21607ms.
[13:59:45.046] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[13:59:45.046] <TB2> INFO: dacScan step from 32 .. 35
[14:00:06.234] <TB2> INFO: Test took 21187ms.
[14:00:06.261] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:00:06.261] <TB2> INFO: dacScan step from 36 .. 39
[14:00:27.473] <TB2> INFO: Test took 21212ms.
[14:00:27.500] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:00:27.500] <TB2> INFO: dacScan step from 40 .. 43
[14:00:48.953] <TB2> INFO: Test took 21453ms.
[14:00:48.980] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:00:48.980] <TB2> INFO: dacScan step from 44 .. 47
[14:01:10.356] <TB2> INFO: Test took 21375ms.
[14:01:10.384] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:01:10.384] <TB2> INFO: dacScan step from 48 .. 51
[14:01:32.106] <TB2> INFO: Test took 21722ms.
[14:01:32.135] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:01:32.135] <TB2> INFO: dacScan step from 52 .. 55
[14:01:53.889] <TB2> INFO: Test took 21754ms.
[14:01:53.918] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:01:53.918] <TB2> INFO: dacScan step from 56 .. 59
[14:02:15.075] <TB2> INFO: Test took 21157ms.
[14:02:15.102] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:02:15.102] <TB2> INFO: dacScan step from 60 .. 63
[14:02:36.803] <TB2> INFO: Test took 21701ms.
[14:02:36.831] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:02:36.831] <TB2> INFO: dacScan step from 64 .. 67
[14:02:58.427] <TB2> INFO: Test took 21596ms.
[14:02:58.458] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:02:58.458] <TB2> INFO: dacScan step from 68 .. 71
[14:03:20.227] <TB2> INFO: Test took 21769ms.
[14:03:20.259] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:03:20.259] <TB2> INFO: dacScan step from 72 .. 75
[14:03:42.114] <TB2> INFO: Test took 21855ms.
[14:03:42.145] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:03:42.146] <TB2> INFO: dacScan step from 76 .. 79
[14:04:04.723] <TB2> INFO: Test took 22577ms.
[14:04:04.766] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:04:04.767] <TB2> INFO: dacScan step from 80 .. 83
[14:04:29.333] <TB2> INFO: Test took 24566ms.
[14:04:29.417] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:04:29.420] <TB2> INFO: dacScan step from 84 .. 87
[14:04:57.531] <TB2> INFO: Test took 28111ms.
[14:04:57.660] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:04:57.668] <TB2> INFO: dacScan step from 88 .. 91
[14:05:27.327] <TB2> INFO: Test took 29659ms.
[14:05:27.492] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:05:27.501] <TB2> INFO: dacScan step from 92 .. 95
[14:05:59.701] <TB2> INFO: Test took 32200ms.
[14:05:59.890] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:05:59.899] <TB2> INFO: dacScan step from 96 .. 99
[14:06:33.382] <TB2> INFO: Test took 33482ms.
[14:06:33.613] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:06:33.624] <TB2> INFO: dacScan step from 100 .. 103


[14:07:08.217] <TB2> INFO: Test took 34593ms.
[14:07:08.452] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:07:08.467] <TB2> INFO: dacScan step from 104 .. 107
[14:07:42.911] <TB2> INFO: Test took 34444ms.
[14:07:43.157] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:07:43.170] <TB2> INFO: dacScan step from 108 .. 111



[14:08:17.059] <TB2> INFO: Test took 33888ms.
[14:08:17.339] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:08:17.354] <TB2> INFO: dacScan step from 112 .. 115



[14:08:51.021] <TB2> INFO: Test took 33667ms.
[14:08:51.248] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:08:51.261] <TB2> INFO: dacScan step from 116 .. 119



[14:09:25.174] <TB2> INFO: Test took 33913ms.
[14:09:25.412] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:09:25.425] <TB2> INFO: dacScan step from 120 .. 123


[14:09:59.792] <TB2> INFO: Test took 34367ms.
[14:10:00.038] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:10:00.050] <TB2> INFO: dacScan step from 124 .. 127





[14:10:33.262] <TB2> INFO: Test took 33212ms.
[14:10:33.499] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:10:33.512] <TB2> INFO: dacScan step from 128 .. 131
[14:11:05.412] <TB2> INFO: Test took 31900ms.
[14:11:05.798] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:11:05.818] <TB2> INFO: dacScan step from 132 .. 135
[14:11:37.431] <TB2> INFO: Test took 31613ms.
[14:11:37.811] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:11:37.832] <TB2> INFO: dacScan step from 136 .. 139
[14:12:11.782] <TB2> INFO: Test took 33950ms.
[14:12:12.093] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:12:12.103] <TB2> INFO: dacScan step from 140 .. 143
[14:12:46.004] <TB2> INFO: Test took 33900ms.
[14:12:46.235] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:12:46.248] <TB2> INFO: dacScan step from 144 .. 147
[14:13:19.915] <TB2> INFO: Test took 33667ms.
[14:13:20.226] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:13:20.241] <TB2> INFO: dacScan step from 148 .. 149
[14:13:37.525] <TB2> INFO: Test took 17284ms.
[14:13:37.657] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:13:37.663] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:39.322] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:40.752] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:42.634] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:44.042] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:45.617] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:47.084] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:48.541] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:50.030] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:51.422] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:52.808] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:54.213] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:55.729] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:57.453] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:13:59.160] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:14:00.889] <TB2> INFO: dumping ASCII scurve output file: SCurveData
[14:14:02.380] <TB2> INFO: PixTestScurves::scurves() done
[14:14:02.380] <TB2> INFO: Vcal mean: 97.35 91.12 90.22 104.83 91.85 84.19 82.19 89.56 84.97 96.15 96.75 92.16 88.59 89.15 104.49 94.08
[14:14:02.380] <TB2> INFO: Vcal RMS: 5.44 5.20 4.69 6.15 5.29 4.44 5.40 5.48 4.64 5.49 5.00 5.86 5.26 5.56 4.98 4.91
[14:14:02.380] <TB2> INFO: PixTestScurves::fullTest() done, duration: 1030 seconds
[14:14:02.451] <TB2> INFO: ######################################################################
[14:14:02.451] <TB2> INFO: PixTestTrim::doTest()
[14:14:02.451] <TB2> INFO: ######################################################################
[14:14:02.453] <TB2> INFO: ----------------------------------------------------------------------
[14:14:02.453] <TB2> INFO: PixTestTrim::trimTest() ntrig = 10, vcal = 35
[14:14:02.453] <TB2> INFO: ----------------------------------------------------------------------
[14:14:02.534] <TB2> INFO: ---> VthrComp thr map (minimal VthrComp)
[14:14:02.534] <TB2> INFO: ---> dac: vthrcomp name: TrimThr0 ntrig: 5 dacrange: 0 .. 159 (20) hits flags = 16 (plus default)
[14:14:02.542] <TB2> INFO: dacScan step from 0 .. 19
[14:14:18.954] <TB2> INFO: Test took 16411ms.
[14:14:18.980] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:14:18.980] <TB2> INFO: dacScan step from 20 .. 39
[14:14:35.149] <TB2> INFO: Test took 16169ms.
[14:14:35.175] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:14:35.175] <TB2> INFO: dacScan step from 40 .. 59
[14:14:51.766] <TB2> INFO: Test took 16590ms.
[14:14:51.788] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:14:51.788] <TB2> INFO: dacScan step from 60 .. 79
[14:15:08.345] <TB2> INFO: Test took 16557ms.
[14:15:08.370] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:15:08.370] <TB2> INFO: dacScan step from 80 .. 99
[14:15:25.594] <TB2> INFO: Test took 17224ms.
[14:15:25.645] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:15:25.652] <TB2> INFO: dacScan step from 100 .. 119
[14:15:47.721] <TB2> INFO: Test took 22069ms.
[14:15:47.894] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:15:47.927] <TB2> INFO: dacScan step from 120 .. 139
[14:16:09.785] <TB2> INFO: Test took 21858ms.
[14:16:09.948] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:16:09.979] <TB2> INFO: dacScan step from 140 .. 159
[14:16:27.025] <TB2> INFO: Test took 17046ms.
[14:16:27.084] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:16:51.428] <TB2> INFO: ROC 0 VthrComp = 100
[14:16:51.429] <TB2> INFO: ROC 1 VthrComp = 95
[14:16:51.429] <TB2> INFO: ROC 2 VthrComp = 94
[14:16:51.429] <TB2> INFO: ROC 3 VthrComp = 103
[14:16:51.429] <TB2> INFO: ROC 4 VthrComp = 92
[14:16:51.429] <TB2> INFO: ROC 5 VthrComp = 85
[14:16:51.429] <TB2> INFO: ROC 6 VthrComp = 88
[14:16:51.429] <TB2> INFO: ROC 7 VthrComp = 92
[14:16:51.429] <TB2> INFO: ROC 8 VthrComp = 87
[14:16:51.429] <TB2> INFO: ROC 9 VthrComp = 96
[14:16:51.429] <TB2> INFO: ROC 10 VthrComp = 95
[14:16:51.430] <TB2> INFO: ROC 11 VthrComp = 92
[14:16:51.430] <TB2> INFO: ROC 12 VthrComp = 92
[14:16:51.430] <TB2> INFO: ROC 13 VthrComp = 89
[14:16:51.430] <TB2> INFO: ROC 14 VthrComp = 105
[14:16:51.430] <TB2> INFO: ROC 15 VthrComp = 95
[14:16:51.430] <TB2> INFO: ---> Vcal thr map (pixel with maximum Vcal thr)
[14:16:51.430] <TB2> INFO: ---> dac: vcal name: TrimThr1 ntrig: 5 dacrange: 0 .. 159 (20) hits flags = 16 (plus default)
[14:16:51.438] <TB2> INFO: dacScan step from 0 .. 19
[14:17:07.225] <TB2> INFO: Test took 15787ms.
[14:17:07.250] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:17:07.250] <TB2> INFO: dacScan step from 20 .. 39
[14:17:24.075] <TB2> INFO: Test took 16825ms.
[14:17:24.109] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:17:24.112] <TB2> INFO: dacScan step from 40 .. 59
[14:17:45.686] <TB2> INFO: Test took 21574ms.
[14:17:45.842] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:17:45.878] <TB2> INFO: dacScan step from 60 .. 79
[14:18:08.543] <TB2> INFO: Test took 22664ms.
[14:18:08.733] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:18:08.783] <TB2> INFO: dacScan step from 80 .. 99
[14:18:31.482] <TB2> INFO: Test took 22699ms.
[14:18:31.648] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:18:31.701] <TB2> INFO: dacScan step from 100 .. 119
[14:18:54.825] <TB2> INFO: Test took 23124ms.
[14:18:54.997] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:18:55.050] <TB2> INFO: dacScan step from 120 .. 139
[14:19:18.039] <TB2> INFO: Test took 22989ms.
[14:19:18.216] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:19:18.268] <TB2> INFO: dacScan step from 140 .. 159
[14:19:40.953] <TB2> INFO: Test took 22685ms.
[14:19:41.134] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:20:09.558] <TB2> INFO: roc 0 with ID = 0 has maximal Vcal 58.5506 for pixel 51/74 mean/min/max = 44.9922/31.3879/58.5965
[14:20:09.558] <TB2> INFO: roc 1 with ID = 1 has maximal Vcal 57.2828 for pixel 11/70 mean/min/max = 44.7229/32.0075/57.4384
[14:20:09.559] <TB2> INFO: roc 2 with ID = 2 has maximal Vcal 55.8657 for pixel 7/3 mean/min/max = 44.4728/32.9401/56.0055
[14:20:09.559] <TB2> INFO: roc 3 with ID = 3 has maximal Vcal 58.5946 for pixel 1/73 mean/min/max = 45.4107/32.1837/58.6376
[14:20:09.560] <TB2> INFO: roc 4 with ID = 4 has maximal Vcal 58.6892 for pixel 12/40 mean/min/max = 46.2976/33.7326/58.8626
[14:20:09.560] <TB2> INFO: roc 5 with ID = 5 has maximal Vcal 56.5351 for pixel 21/2 mean/min/max = 44.7755/32.8901/56.661
[14:20:09.560] <TB2> INFO: roc 6 with ID = 6 has maximal Vcal 59.0266 for pixel 9/79 mean/min/max = 46.1486/33.1826/59.1147
[14:20:09.561] <TB2> INFO: roc 7 with ID = 7 has maximal Vcal 60.0917 for pixel 3/41 mean/min/max = 46.5094/32.8735/60.1452
[14:20:09.561] <TB2> INFO: roc 8 with ID = 8 has maximal Vcal 56.5805 for pixel 2/61 mean/min/max = 44.7915/32.9806/56.6025
[14:20:09.561] <TB2> INFO: roc 9 with ID = 9 has maximal Vcal 58.5177 for pixel 10/1 mean/min/max = 45.0968/31.5959/58.5978
[14:20:09.562] <TB2> INFO: roc 10 with ID = 10 has maximal Vcal 59.7973 for pixel 0/25 mean/min/max = 46.4075/32.976/59.8389
[14:20:09.562] <TB2> INFO: roc 11 with ID = 11 has maximal Vcal 62.3401 for pixel 23/14 mean/min/max = 47.2925/32.2261/62.359
[14:20:09.562] <TB2> INFO: roc 12 with ID = 12 has maximal Vcal 58.6467 for pixel 3/3 mean/min/max = 45.8867/32.8155/58.958
[14:20:09.563] <TB2> INFO: roc 13 with ID = 13 has maximal Vcal 61.9912 for pixel 0/8 mean/min/max = 47.8457/33.613/62.0784
[14:20:09.563] <TB2> INFO: roc 14 with ID = 14 has maximal Vcal 59.5185 for pixel 25/15 mean/min/max = 47.0436/34.5552/59.532
[14:20:09.564] <TB2> INFO: roc 15 with ID = 15 has maximal Vcal 57.1097 for pixel 16/39 mean/min/max = 44.9598/32.5861/57.3334
[14:20:09.564] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[14:21:58.711] <TB2> INFO: Test took 109147ms.
[14:22:00.122] <TB2> INFO: ---> dac: vcal name: TrimThr2 ntrig: 10 dacrange: 0 .. 199 (20) hits flags = 16 (plus default)
[14:22:00.130] <TB2> INFO: dacScan step from 0 .. 19
[14:22:25.955] <TB2> INFO: Test took 25825ms.
[14:22:26.009] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:22:26.012] <TB2> INFO: dacScan step from 20 .. 39
[14:23:00.078] <TB2> INFO: Test took 34066ms.
[14:23:00.336] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:23:00.369] <TB2> INFO: dacScan step from 40 .. 59


[14:23:37.358] <TB2> INFO: Test took 36989ms.
[14:23:37.625] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:23:37.682] <TB2> INFO: dacScan step from 60 .. 79
[14:24:12.789] <TB2> INFO: Test took 35107ms.
[14:24:13.239] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:24:13.331] <TB2> INFO: dacScan step from 80 .. 99


[14:24:51.073] <TB2> INFO: Test took 37742ms.
[14:24:51.346] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:24:51.400] <TB2> INFO: dacScan step from 100 .. 119


[14:25:28.666] <TB2> INFO: Test took 37266ms.
[14:25:28.941] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:25:28.994] <TB2> INFO: dacScan step from 120 .. 139


[14:26:06.727] <TB2> INFO: Test took 37733ms.
[14:26:07.067] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:26:07.128] <TB2> INFO: dacScan step from 140 .. 159


[14:26:44.893] <TB2> INFO: Test took 37765ms.
[14:26:45.166] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:26:45.217] <TB2> INFO: dacScan step from 160 .. 179


[14:27:22.904] <TB2> INFO: Test took 37687ms.
[14:27:23.288] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:27:23.350] <TB2> INFO: dacScan step from 180 .. 199


[14:28:00.967] <TB2> INFO: Test took 37616ms.
[14:28:01.236] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:28:27.704] <TB2> INFO: ---> TrimStepCorr4 extremal thresholds: 0.010486 .. 255.000000
[14:28:27.826] <TB2> INFO: ---> dac: vcal name: trimStepCorr4 ntrig: 4 dacrange: 0 .. 255 (20) hits flags = 16 (plus default)
[14:28:27.837] <TB2> INFO: dacScan step from 0 .. 19
[14:28:41.997] <TB2> INFO: Test took 14160ms.
[14:28:42.015] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:28:42.016] <TB2> INFO: dacScan step from 20 .. 39
[14:28:58.439] <TB2> INFO: Test took 16423ms.
[14:28:58.530] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:28:58.545] <TB2> INFO: dacScan step from 40 .. 59
[14:29:18.395] <TB2> INFO: Test took 19850ms.
[14:29:18.546] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:29:18.603] <TB2> INFO: dacScan step from 60 .. 79
[14:29:37.632] <TB2> INFO: Test took 19028ms.
[14:29:37.773] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:29:37.828] <TB2> INFO: dacScan step from 80 .. 99
[14:29:57.259] <TB2> INFO: Test took 19431ms.
[14:29:57.436] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:29:57.494] <TB2> INFO: dacScan step from 100 .. 119
[14:30:16.176] <TB2> INFO: Test took 18682ms.
[14:30:16.348] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:30:16.400] <TB2> INFO: dacScan step from 120 .. 139
[14:30:35.792] <TB2> INFO: Test took 19392ms.
[14:30:35.964] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:30:36.020] <TB2> INFO: dacScan step from 140 .. 159
[14:30:54.945] <TB2> INFO: Test took 18925ms.
[14:30:55.126] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:30:55.190] <TB2> INFO: dacScan step from 160 .. 179
[14:31:14.467] <TB2> INFO: Test took 19277ms.
[14:31:14.611] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:31:14.663] <TB2> INFO: dacScan step from 180 .. 199
[14:31:35.364] <TB2> INFO: Test took 20701ms.
[14:31:35.518] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:31:35.576] <TB2> INFO: dacScan step from 200 .. 219
[14:31:54.648] <TB2> INFO: Test took 19072ms.
[14:31:54.801] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:31:54.860] <TB2> INFO: dacScan step from 220 .. 239
[14:32:13.953] <TB2> INFO: Test took 19093ms.
[14:32:14.148] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:32:14.215] <TB2> INFO: dacScan step from 240 .. 255
[14:32:30.492] <TB2> INFO: Test took 16277ms.
[14:32:30.613] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:33:03.511] <TB2> INFO: ---> TrimStepCorr2 extremal thresholds: 13.500076 .. 54.062614
[14:33:03.593] <TB2> INFO: ---> dac: vcal name: trimStepCorr2 ntrig: 4 dacrange: 3 .. 64 (20) hits flags = 16 (plus default)
[14:33:03.602] <TB2> INFO: dacScan step from 3 .. 22
[14:33:17.850] <TB2> INFO: Test took 14248ms.
[14:33:17.877] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:33:17.877] <TB2> INFO: dacScan step from 23 .. 42
[14:33:35.278] <TB2> INFO: Test took 17401ms.
[14:33:35.383] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:33:35.406] <TB2> INFO: dacScan step from 43 .. 62
[14:33:55.337] <TB2> INFO: Test took 19931ms.
[14:33:55.527] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:33:55.583] <TB2> INFO: dacScan step from 63 .. 64
[14:34:00.074] <TB2> INFO: Test took 4491ms.
[14:34:00.093] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:34:20.288] <TB2> INFO: ---> TrimStepCorr1a extremal thresholds: 1.990008 .. 66.580995
[14:34:20.372] <TB2> INFO: ---> dac: vcal name: trimStepCorr1a ntrig: 4 dacrange: 1 .. 76 (20) hits flags = 16 (plus default)
[14:34:20.381] <TB2> INFO: dacScan step from 1 .. 20
[14:34:35.041] <TB2> INFO: Test took 14660ms.
[14:34:35.069] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:34:35.069] <TB2> INFO: dacScan step from 21 .. 40
[14:34:51.949] <TB2> INFO: Test took 16880ms.
[14:34:52.047] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:34:52.065] <TB2> INFO: dacScan step from 41 .. 60
[14:35:11.929] <TB2> INFO: Test took 19864ms.
[14:35:12.088] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:35:12.147] <TB2> INFO: dacScan step from 61 .. 76
[14:35:28.685] <TB2> INFO: Test took 16538ms.
[14:35:28.805] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:35:49.479] <TB2> INFO: ---> TrimStepCorr1b extremal thresholds: 1.500117 .. 66.580995
[14:35:49.573] <TB2> INFO: ---> dac: vcal name: trimStepCorr1b ntrig: 4 dacrange: 1 .. 76 (20) hits flags = 16 (plus default)
[14:35:49.583] <TB2> INFO: dacScan step from 1 .. 20
[14:36:04.119] <TB2> INFO: Test took 14536ms.
[14:36:04.144] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:36:04.144] <TB2> INFO: dacScan step from 21 .. 40
[14:36:20.490] <TB2> INFO: Test took 16346ms.
[14:36:20.575] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:36:20.593] <TB2> INFO: dacScan step from 41 .. 60
[14:36:40.689] <TB2> INFO: Test took 20096ms.
[14:36:40.854] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:36:40.914] <TB2> INFO: dacScan step from 61 .. 76
[14:36:56.942] <TB2> INFO: Test took 16028ms.
[14:36:57.056] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:37:17.432] <TB2> INFO: ---> TrimThrFinal extremal thresholds: 15 .. 55
[14:37:17.432] <TB2> INFO: ---> dac: vcal name: TrimThrFinal ntrig: 10 dacrange: 15 .. 55 (20) hits flags = 16 (plus default)
[14:37:17.440] <TB2> INFO: dacScan step from 15 .. 34
[14:37:44.013] <TB2> INFO: Test took 26573ms.
[14:37:44.099] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:37:44.113] <TB2> INFO: dacScan step from 35 .. 54



[14:38:19.898] <TB2> INFO: Test took 35785ms.
[14:38:20.192] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:38:20.243] <TB2> INFO: dacScan step from 55 .. 55
[14:38:24.790] <TB2> INFO: Test took 4547ms.
[14:38:24.810] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:38:39.099] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C0.dat
[14:38:39.099] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C1.dat
[14:38:39.099] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C2.dat
[14:38:39.099] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C3.dat
[14:38:39.100] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C4.dat
[14:38:39.100] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C5.dat
[14:38:39.100] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C6.dat
[14:38:39.100] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C7.dat
[14:38:39.101] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C8.dat
[14:38:39.101] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C9.dat
[14:38:39.101] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C10.dat
[14:38:39.102] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C11.dat
[14:38:39.102] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C12.dat
[14:38:39.102] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C13.dat
[14:38:39.102] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C14.dat
[14:38:39.103] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C15.dat
[14:38:39.103] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C0.dat
[14:38:39.118] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C1.dat
[14:38:39.128] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C2.dat
[14:38:39.137] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C3.dat
[14:38:39.147] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C4.dat
[14:38:39.157] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C5.dat
[14:38:39.167] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C6.dat
[14:38:39.177] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C7.dat
[14:38:39.187] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C8.dat
[14:38:39.197] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C9.dat
[14:38:39.207] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C10.dat
[14:38:39.217] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C11.dat
[14:38:39.227] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C12.dat
[14:38:39.237] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C13.dat
[14:38:39.247] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C14.dat
[14:38:39.257] <TB2> INFO: write trim parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//trimParameters35_C15.dat
[14:38:39.267] <TB2> INFO: PixTestTrim::trimTest() done
[14:38:39.267] <TB2> INFO: vtrim: 110 106 104 109 100 100 90 169 177 107 112 118 109 107 114 106
[14:38:39.267] <TB2> INFO: vthrcomp: 100 95 94 103 92 85 88 92 87 96 95 92 92 89 105 95
[14:38:39.267] <TB2> INFO: vcal mean: 35.07 35.11 35.09 35.08 35.09 35.12 35.04 34.98 35.08 35.02 35.09 35.11 35.04 35.06 35.13 35.10
[14:38:39.267] <TB2> INFO: vcal RMS: 1.06 1.12 1.04 1.13 1.06 1.07 0.96 2.02 1.49 1.15 1.05 1.22 1.13 1.19 1.16 1.09
[14:38:39.267] <TB2> INFO: bits mean: 10.35 9.91 10.02 10.14 9.32 10.03 8.63 11.42 12.04 9.97 9.53 9.88 9.77 9.21 9.35 10.17
[14:38:39.267] <TB2> INFO: bits RMS: 2.45 2.64 2.42 2.39 2.54 2.42 2.84 1.68 1.44 2.59 2.58 2.35 2.49 2.51 2.38 2.42
[14:38:39.275] <TB2> INFO: ----------------------------------------------------------------------
[14:38:39.275] <TB2> INFO: PixTestTrim::trimBitTest() ntrig = 10, vtrims = 254 126 63 32
[14:38:39.275] <TB2> INFO: ----------------------------------------------------------------------
[14:38:39.278] <TB2> INFO: ---> dac: Vcal name: TrimBitsThr0 ntrig: 10 dacrange: 0 .. 199 (20) hits flags = 16 (plus default)
[14:38:39.293] <TB2> INFO: dacScan step from 0 .. 19
[14:39:04.495] <TB2> INFO: Test took 25202ms.
[14:39:04.532] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:39:04.532] <TB2> INFO: dacScan step from 20 .. 39
[14:39:29.654] <TB2> INFO: Test took 25122ms.
[14:39:29.693] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:39:29.693] <TB2> INFO: dacScan step from 40 .. 59
[14:39:54.491] <TB2> INFO: Test took 24798ms.
[14:39:54.531] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:39:54.531] <TB2> INFO: dacScan step from 60 .. 79
[14:40:19.607] <TB2> INFO: Test took 25076ms.
[14:40:19.644] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:40:19.644] <TB2> INFO: dacScan step from 80 .. 99
[14:40:44.826] <TB2> INFO: Test took 25182ms.
[14:40:44.866] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:40:44.867] <TB2> INFO: dacScan step from 100 .. 119
[14:41:12.920] <TB2> INFO: Test took 28053ms.
[14:41:13.058] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:41:13.070] <TB2> INFO: dacScan step from 120 .. 139
[14:41:48.731] <TB2> INFO: Test took 35661ms.
[14:41:49.104] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:41:49.156] <TB2> INFO: dacScan step from 140 .. 159


[14:42:24.895] <TB2> INFO: Test took 35739ms.
[14:42:25.173] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:42:25.235] <TB2> INFO: dacScan step from 160 .. 179
[14:43:03.775] <TB2> INFO: Test took 38541ms.
[14:43:04.046] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:43:04.100] <TB2> INFO: dacScan step from 180 .. 199
[14:43:43.363] <TB2> INFO: Test took 39263ms.
[14:43:43.677] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:44:10.106] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim14 ntrig: 10 dacrange: 0 .. 171 (20) hits flags = 16 (plus default)
[14:44:10.114] <TB2> INFO: dacScan step from 0 .. 19
[14:44:35.412] <TB2> INFO: Test took 25298ms.
[14:44:35.446] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:44:35.446] <TB2> INFO: dacScan step from 20 .. 39
[14:44:59.454] <TB2> INFO: Test took 24008ms.
[14:44:59.489] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:44:59.489] <TB2> INFO: dacScan step from 40 .. 59
[14:45:23.266] <TB2> INFO: Test took 23777ms.
[14:45:23.314] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:45:23.314] <TB2> INFO: dacScan step from 60 .. 79
[14:45:48.482] <TB2> INFO: Test took 25168ms.
[14:45:48.526] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:45:48.526] <TB2> INFO: dacScan step from 80 .. 99
[14:46:14.541] <TB2> INFO: Test took 26015ms.
[14:46:14.614] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:46:14.618] <TB2> INFO: dacScan step from 100 .. 119
[14:46:47.228] <TB2> INFO: Test took 32610ms.
[14:46:47.459] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:46:47.485] <TB2> INFO: dacScan step from 120 .. 139



[14:47:25.586] <TB2> INFO: Test took 38101ms.
[14:47:25.901] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:47:25.952] <TB2> INFO: dacScan step from 140 .. 159


[14:48:03.840] <TB2> INFO: Test took 37888ms.
[14:48:04.124] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:48:04.178] <TB2> INFO: dacScan step from 160 .. 171
[14:48:27.084] <TB2> INFO: Test took 22906ms.
[14:48:27.289] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:48:51.296] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim13 ntrig: 10 dacrange: 0 .. 158 (20) hits flags = 16 (plus default)
[14:48:51.306] <TB2> INFO: dacScan step from 0 .. 19
[14:49:15.306] <TB2> INFO: Test took 24000ms.
[14:49:15.342] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:49:15.342] <TB2> INFO: dacScan step from 20 .. 39
[14:49:40.758] <TB2> INFO: Test took 25416ms.
[14:49:40.796] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:49:40.796] <TB2> INFO: dacScan step from 40 .. 59
[14:50:05.722] <TB2> INFO: Test took 24926ms.
[14:50:05.758] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:50:05.758] <TB2> INFO: dacScan step from 60 .. 79
[14:50:29.736] <TB2> INFO: Test took 23978ms.
[14:50:29.773] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:50:29.773] <TB2> INFO: dacScan step from 80 .. 99
[14:50:56.051] <TB2> INFO: Test took 26278ms.
[14:50:56.113] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:50:56.117] <TB2> INFO: dacScan step from 100 .. 119
[14:51:31.268] <TB2> INFO: Test took 35151ms.
[14:51:31.507] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:51:31.534] <TB2> INFO: dacScan step from 120 .. 139


[14:52:08.276] <TB2> INFO: Test took 36741ms.
[14:52:08.554] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:52:08.611] <TB2> INFO: dacScan step from 140 .. 158



[14:52:43.818] <TB2> INFO: Test took 35207ms.
[14:52:44.091] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:53:08.760] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim11 ntrig: 10 dacrange: 0 .. 158 (20) hits flags = 16 (plus default)
[14:53:08.769] <TB2> INFO: dacScan step from 0 .. 19
[14:53:33.936] <TB2> INFO: Test took 25167ms.
[14:53:33.972] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:53:33.972] <TB2> INFO: dacScan step from 20 .. 39
[14:53:59.493] <TB2> INFO: Test took 25521ms.
[14:53:59.533] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:53:59.533] <TB2> INFO: dacScan step from 40 .. 59
[14:54:24.245] <TB2> INFO: Test took 24711ms.
[14:54:24.280] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:54:24.280] <TB2> INFO: dacScan step from 60 .. 79
[14:54:48.074] <TB2> INFO: Test took 23794ms.
[14:54:48.110] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:54:48.110] <TB2> INFO: dacScan step from 80 .. 99
[14:55:14.420] <TB2> INFO: Test took 26310ms.
[14:55:14.491] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:55:14.495] <TB2> INFO: dacScan step from 100 .. 119
[14:55:49.872] <TB2> INFO: Test took 35377ms.
[14:55:50.116] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:55:50.152] <TB2> INFO: dacScan step from 120 .. 139
[14:56:27.586] <TB2> INFO: Test took 37434ms.
[14:56:27.888] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:56:27.940] <TB2> INFO: dacScan step from 140 .. 158





[14:57:03.833] <TB2> INFO: Test took 35892ms.
[14:57:04.104] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:57:29.130] <TB2> INFO: ---> dac: Vcal name: TrimThr_trim7 ntrig: 10 dacrange: 0 .. 157 (20) hits flags = 16 (plus default)
[14:57:29.138] <TB2> INFO: dacScan step from 0 .. 19
[14:57:54.291] <TB2> INFO: Test took 25153ms.
[14:57:54.332] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:57:54.332] <TB2> INFO: dacScan step from 20 .. 39
[14:58:19.324] <TB2> INFO: Test took 24992ms.
[14:58:19.361] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:58:19.361] <TB2> INFO: dacScan step from 40 .. 59
[14:58:44.872] <TB2> INFO: Test took 25511ms.
[14:58:44.909] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:58:44.909] <TB2> INFO: dacScan step from 60 .. 79
[14:59:09.937] <TB2> INFO: Test took 25028ms.
[14:59:09.981] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:59:09.981] <TB2> INFO: dacScan step from 80 .. 99
[14:59:36.598] <TB2> INFO: Test took 26617ms.
[14:59:36.666] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[14:59:36.670] <TB2> INFO: dacScan step from 100 .. 119
[15:00:11.640] <TB2> INFO: Test took 34970ms.
[15:00:11.873] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:00:11.899] <TB2> INFO: dacScan step from 120 .. 139



[15:00:49.771] <TB2> INFO: Test took 37872ms.
[15:00:50.046] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:00:50.099] <TB2> INFO: dacScan step from 140 .. 157
[15:01:25.031] <TB2> INFO: Test took 34932ms.
[15:01:25.316] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:01:49.887] <TB2> INFO: PixTestTrim::trimBitTest() done
[15:01:49.888] <TB2> INFO: PixTestTrim::doTest() done, duration: 2867 seconds
[15:01:50.574] <TB2> INFO: ######################################################################
[15:01:50.574] <TB2> INFO: PixTestPhOptimization::doTest() Ntrig = 10
[15:01:50.574] <TB2> INFO: ######################################################################
[15:01:54.321] <TB2> INFO: Test took 3746ms.
[15:01:54.344] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:01:58.186] <TB2> INFO: Test took 3645ms.
[15:01:58.253] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:02:01.982] <TB2> INFO: Test took 3720ms.
[15:02:02.062] <TB2> INFO: Fetched DAQ statistics. Counters are being reset now.
[15:02:02.070] <TB2> INFO: The DUT currently contains the following objects:
[15:02:02.070] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:02.070] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:02.070] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:02.070] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:02.070] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:02.070] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.172] <TB2> INFO: Test took 1102ms.
[15:02:03.173] <TB2> INFO: The DUT currently contains the following objects:
[15:02:03.173] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:03.173] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:03.173] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:03.173] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:03.173] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:03.173] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.282] <TB2> INFO: Test took 1109ms.
[15:02:04.283] <TB2> INFO: The DUT currently contains the following objects:
[15:02:04.284] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:04.284] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:04.284] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:04.284] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:04.284] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:04.284] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.420] <TB2> INFO: Test took 1136ms.
[15:02:05.421] <TB2> INFO: The DUT currently contains the following objects:
[15:02:05.421] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:05.421] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:05.421] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:05.421] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:05.421] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.421] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.421] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.421] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.421] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.421] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.421] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.421] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.421] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.422] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.422] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.422] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.422] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.422] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.422] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:05.422] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.543] <TB2> INFO: Test took 1121ms.
[15:02:06.545] <TB2> INFO: The DUT currently contains the following objects:
[15:02:06.545] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:06.545] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:06.545] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:06.545] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:06.545] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.545] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.545] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.545] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.545] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.545] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.545] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.545] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.546] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.546] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.546] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.546] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.546] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.546] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.546] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:06.546] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.683] <TB2> INFO: Test took 1137ms.
[15:02:07.684] <TB2> INFO: The DUT currently contains the following objects:
[15:02:07.684] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:07.684] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:07.684] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:07.684] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:07.684] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.684] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.684] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.684] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.684] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.685] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.685] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.685] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.685] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.685] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.685] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.685] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.685] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.685] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.685] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:07.685] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.807] <TB2> INFO: Test took 1122ms.
[15:02:08.808] <TB2> INFO: The DUT currently contains the following objects:
[15:02:08.808] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:08.808] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:08.808] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:08.808] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:08.808] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.808] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.809] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:08.809] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.934] <TB2> INFO: Test took 1125ms.
[15:02:09.935] <TB2> INFO: The DUT currently contains the following objects:
[15:02:09.935] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:09.935] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:09.935] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:09.935] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:09.935] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.935] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.935] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:09.936] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.071] <TB2> INFO: Test took 1135ms.
[15:02:11.073] <TB2> INFO: The DUT currently contains the following objects:
[15:02:11.073] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:11.073] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:11.073] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:11.073] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:11.073] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.073] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.074] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:11.074] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.180] <TB2> INFO: Test took 1106ms.
[15:02:12.182] <TB2> INFO: The DUT currently contains the following objects:
[15:02:12.182] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:12.182] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:12.182] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:12.182] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:12.182] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.182] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.182] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.182] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.182] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.182] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.182] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.182] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.182] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.182] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.182] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.183] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.183] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.183] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.183] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:12.183] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.288] <TB2> INFO: Test took 1105ms.
[15:02:13.289] <TB2> INFO: The DUT currently contains the following objects:
[15:02:13.289] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:13.289] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:13.289] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:13.289] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:13.289] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.289] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.289] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:13.290] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.397] <TB2> INFO: Test took 1107ms.
[15:02:14.399] <TB2> INFO: The DUT currently contains the following objects:
[15:02:14.399] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:14.399] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:14.399] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:14.399] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:14.399] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.399] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.400] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:14.400] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.506] <TB2> INFO: Test took 1106ms.
[15:02:15.507] <TB2> INFO: The DUT currently contains the following objects:
[15:02:15.507] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:15.507] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:15.507] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:15.507] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:15.507] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.507] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.507] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.507] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.507] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.508] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.508] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.508] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.508] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.508] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.508] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.508] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.508] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.508] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.508] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:15.508] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.614] <TB2> INFO: Test took 1106ms.
[15:02:16.616] <TB2> INFO: The DUT currently contains the following objects:
[15:02:16.616] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:16.616] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:16.616] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:16.616] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:16.616] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:16.616] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.723] <TB2> INFO: Test took 1107ms.
[15:02:17.724] <TB2> INFO: The DUT currently contains the following objects:
[15:02:17.724] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:17.724] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:17.724] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:17.724] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:17.724] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.724] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.724] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.724] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.724] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.725] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.725] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.725] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.725] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.725] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.725] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.725] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.725] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.725] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.725] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:17.725] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.861] <TB2> INFO: Test took 1136ms.
[15:02:18.863] <TB2> INFO: The DUT currently contains the following objects:
[15:02:18.863] <TB2> INFO: 2 TBM Cores tbm09c (2 ON)
[15:02:18.863] <TB2> INFO: TBM Core alpha (0): 7 registers set
[15:02:18.863] <TB2> INFO: TBM Core beta (1): 7 registers set
[15:02:18.863] <TB2> INFO: 16 ROCs psi46digv21respin (1 ON) with 4160 pixelConfigs
[15:02:18.863] <TB2> INFO: ROC 0: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 1: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 2: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 3: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 4: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 5: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 6: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 7: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 8: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 9: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 10: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 11: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 12: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 13: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.863] <TB2> INFO: ROC 14: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:18.864] <TB2> INFO: ROC 15: 19 DACs set, Pixels: 4159 masked, 1 active.
[15:02:19.998] <TB2> INFO: Test took 1134ms.
[15:02:20.002] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:06:36.738] <TB2> INFO: Test took 256736ms.
[15:06:38.157] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:10:42.258] <TB2> INFO: Test took 244101ms.
[15:10:43.810] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.816] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.823] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.829] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.836] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.842] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.849] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.855] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.861] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.868] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.874] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.881] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.887] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.893] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.900] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.906] <TB2> INFO: safety margin for low PH: adding 1, margin is now 21
[15:10:43.913] <TB2> INFO: safety margin for low PH: adding 2, margin is now 22
[15:10:43.919] <TB2> INFO: safety margin for low PH: adding 3, margin is now 23
[15:10:43.925] <TB2> INFO: safety margin for low PH: adding 0, margin is now 20
[15:10:43.960] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C0.dat
[15:10:43.960] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C1.dat
[15:10:43.960] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C2.dat
[15:10:43.960] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C3.dat
[15:10:43.960] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C4.dat
[15:10:43.960] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C5.dat
[15:10:43.960] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C6.dat
[15:10:43.969] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C7.dat
[15:10:43.969] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C8.dat
[15:10:43.969] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C9.dat
[15:10:43.969] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C10.dat
[15:10:43.970] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C11.dat
[15:10:43.970] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C12.dat
[15:10:43.970] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C13.dat
[15:10:43.970] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C14.dat
[15:10:43.970] <TB2> INFO: write dac parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//dacParameters35_C15.dat
[15:10:47.536] <TB2> INFO: Test took 3563ms.
[15:10:51.468] <TB2> INFO: Test took 3671ms.
[15:10:55.309] <TB2> INFO: Test took 3578ms.
[15:10:55.576] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:10:56.502] <TB2> INFO: Test took 926ms.
[15:10:56.504] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:10:57.603] <TB2> INFO: Test took 1099ms.
[15:10:57.605] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:10:58.719] <TB2> INFO: Test took 1114ms.
[15:10:58.721] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:10:59.835] <TB2> INFO: Test took 1114ms.
[15:10:59.837] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:00.967] <TB2> INFO: Test took 1130ms.
[15:11:00.969] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:02.069] <TB2> INFO: Test took 1100ms.
[15:11:02.071] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:03.170] <TB2> INFO: Test took 1099ms.
[15:11:03.172] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:04.301] <TB2> INFO: Test took 1129ms.
[15:11:04.302] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:05.416] <TB2> INFO: Test took 1114ms.
[15:11:05.418] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:06.532] <TB2> INFO: Test took 1114ms.
[15:11:06.533] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:07.662] <TB2> INFO: Test took 1129ms.
[15:11:07.664] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:08.763] <TB2> INFO: Test took 1099ms.
[15:11:08.765] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:09.879] <TB2> INFO: Test took 1114ms.
[15:11:09.880] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:10.980] <TB2> INFO: Test took 1100ms.
[15:11:10.982] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:12.082] <TB2> INFO: Test took 1100ms.
[15:11:12.083] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:13.211] <TB2> INFO: Test took 1128ms.
[15:11:13.213] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:14.327] <TB2> INFO: Test took 1114ms.
[15:11:14.329] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:15.443] <TB2> INFO: Test took 1114ms.
[15:11:15.445] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:16.559] <TB2> INFO: Test took 1114ms.
[15:11:16.560] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:17.660] <TB2> INFO: Test took 1100ms.
[15:11:17.662] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:18.776] <TB2> INFO: Test took 1114ms.
[15:11:18.778] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:19.877] <TB2> INFO: Test took 1099ms.
[15:11:19.879] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:21.009] <TB2> INFO: Test took 1130ms.
[15:11:21.011] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:22.125] <TB2> INFO: Test took 1114ms.
[15:11:22.127] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:23.241] <TB2> INFO: Test took 1114ms.
[15:11:23.243] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:24.372] <TB2> INFO: Test took 1129ms.
[15:11:24.373] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:25.473] <TB2> INFO: Test took 1100ms.
[15:11:25.475] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:26.575] <TB2> INFO: Test took 1100ms.
[15:11:26.577] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:27.705] <TB2> INFO: Test took 1128ms.
[15:11:27.707] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:28.835] <TB2> INFO: Test took 1129ms.
[15:11:28.837] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:29.980] <TB2> INFO: Test took 1143ms.
[15:11:29.981] <TB2> INFO: Not all ROCs have their pixels configured the same way. Running in FLAG_FORCE_SERIAL mode.
[15:11:31.110] <TB2> INFO: Test took 1129ms.
[15:11:31.612] <TB2> INFO: PixTestPhOptimization::doTest() done, duration: 581 seconds
[15:11:31.612] <TB2> INFO: PH scale (per ROC): 67 82 79 76 68 75 78 77 78 75 78 76 80 78 74 74
[15:11:31.612] <TB2> INFO: PH offset (per ROC): 178 166 167 174 171 159 177 177 172 185 175 164 181 193 176 164
[15:11:31.778] <TB2> INFO: ######################################################################
[15:11:31.778] <TB2> INFO: PixTestGainPedestal::fullTest() ntrig = 10
[15:11:31.778] <TB2> INFO: ######################################################################
[15:11:31.787] <TB2> INFO: scanning low vcal = 10
[15:11:35.634] <TB2> INFO: Test took 3847ms.
[15:11:35.636] <TB2> INFO: scanning low vcal = 20
[15:11:39.524] <TB2> INFO: Test took 3888ms.
[15:11:39.527] <TB2> INFO: scanning low vcal = 30
[15:11:43.495] <TB2> INFO: Test took 3968ms.
[15:11:43.502] <TB2> INFO: scanning low vcal = 40
[15:11:48.099] <TB2> INFO: Test took 4597ms.
[15:11:48.154] <TB2> INFO: scanning low vcal = 50
[15:11:52.567] <TB2> INFO: Test took 4413ms.
[15:11:52.620] <TB2> INFO: scanning low vcal = 60
[15:11:57.015] <TB2> INFO: Test took 4395ms.
[15:11:57.068] <TB2> INFO: scanning low vcal = 70
[15:12:01.526] <TB2> INFO: Test took 4457ms.
[15:12:01.580] <TB2> INFO: scanning low vcal = 80
[15:12:06.080] <TB2> INFO: Test took 4500ms.
[15:12:06.133] <TB2> INFO: scanning low vcal = 90
[15:12:10.575] <TB2> INFO: Test took 4442ms.
[15:12:10.628] <TB2> INFO: scanning low vcal = 100
[15:12:15.200] <TB2> INFO: Test took 4572ms.
[15:12:15.254] <TB2> INFO: scanning low vcal = 110
[15:12:19.801] <TB2> INFO: Test took 4547ms.
[15:12:19.854] <TB2> INFO: scanning low vcal = 120
[15:12:24.353] <TB2> INFO: Test took 4498ms.
[15:12:24.407] <TB2> INFO: scanning low vcal = 130
[15:12:28.902] <TB2> INFO: Test took 4495ms.
[15:12:28.955] <TB2> INFO: scanning low vcal = 140
[15:12:33.425] <TB2> INFO: Test took 4469ms.
[15:12:33.478] <TB2> INFO: scanning low vcal = 150
[15:12:37.977] <TB2> INFO: Test took 4499ms.
[15:12:38.031] <TB2> INFO: scanning low vcal = 160
[15:12:42.528] <TB2> INFO: Test took 4497ms.
[15:12:42.581] <TB2> INFO: scanning low vcal = 170
[15:12:47.088] <TB2> INFO: Test took 4507ms.
[15:12:47.142] <TB2> INFO: scanning low vcal = 180
[15:12:51.665] <TB2> INFO: Test took 4523ms.
[15:12:51.718] <TB2> INFO: scanning low vcal = 190
[15:12:56.329] <TB2> INFO: Test took 4611ms.
[15:12:56.382] <TB2> INFO: scanning low vcal = 200
[15:13:00.813] <TB2> INFO: Test took 4431ms.
[15:13:00.867] <TB2> INFO: scanning low vcal = 210
[15:13:05.395] <TB2> INFO: Test took 4528ms.
[15:13:05.448] <TB2> INFO: scanning low vcal = 220
[15:13:09.934] <TB2> INFO: Test took 4485ms.
[15:13:09.987] <TB2> INFO: scanning low vcal = 230
[15:13:14.499] <TB2> INFO: Test took 4512ms.
[15:13:14.552] <TB2> INFO: scanning low vcal = 240
[15:13:18.963] <TB2> INFO: Test took 4411ms.
[15:13:19.016] <TB2> INFO: scanning low vcal = 250
[15:13:23.505] <TB2> INFO: Test took 4489ms.
[15:13:23.560] <TB2> INFO: scanning high vcal = 30 (= 210 in low range)
[15:13:28.077] <TB2> INFO: Test took 4517ms.
[15:13:28.130] <TB2> INFO: scanning high vcal = 50 (= 350 in low range)
[15:13:32.642] <TB2> INFO: Test took 4512ms.
[15:13:32.695] <TB2> INFO: scanning high vcal = 70 (= 490 in low range)
[15:13:37.120] <TB2> INFO: Test took 4425ms.
[15:13:37.173] <TB2> INFO: scanning high vcal = 90 (= 630 in low range)
[15:13:41.728] <TB2> INFO: Test took 4554ms.
[15:13:41.781] <TB2> INFO: scanning high vcal = 200 (= 1400 in low range)
[15:13:46.180] <TB2> INFO: Test took 4399ms.
[15:13:46.650] <TB2> INFO: PixTestGainPedestal::measure() done
[15:14:17.778] <TB2> INFO: PixTestGainPedestal::fit() done
[15:14:17.778] <TB2> INFO: non-linearity mean: 0.949 0.954 0.956 0.962 0.948 0.953 0.960 0.957 0.962 0.955 0.965 0.962 0.957 0.960 0.962 0.960
[15:14:17.778] <TB2> INFO: non-linearity RMS: 0.007 0.009 0.007 0.006 0.009 0.007 0.006 0.008 0.008 0.008 0.006 0.006 0.008 0.006 0.005 0.006
[15:14:17.778] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C0.dat
[15:14:17.796] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C1.dat
[15:14:17.814] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C2.dat
[15:14:17.832] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C3.dat
[15:14:17.850] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C4.dat
[15:14:17.867] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C5.dat
[15:14:17.885] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C6.dat
[15:14:17.903] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C7.dat
[15:14:17.921] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C8.dat
[15:14:17.938] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C9.dat
[15:14:17.956] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C10.dat
[15:14:17.974] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C11.dat
[15:14:17.991] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C12.dat
[15:14:18.009] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C13.dat
[15:14:18.027] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C14.dat
[15:14:18.045] <TB2> INFO: write gain/ped parameters into /usr/local/coldboxDATA/M2051_FullQualification_2015-07-28_10h11m_1438071093//004_FulltestPxar_p17//phCalibrationFitErr35_C15.dat
[15:14:18.062] <TB2> INFO: PixTestGainPedestal::doTest() done, duration: 166 seconds
[15:14:18.068] <TB2> INFO: enter test to run
[15:14:18.068] <TB2> INFO: test: exit no parameter change
[15:14:18.648] <TB2> QUIET: Connection to board 156 closed.
[15:14:18.728] <TB2> INFO: pXar: this is the end, my friend